公开(公告)号：US20200111645A1

公开(公告)日：2020-04-09

申请号：US16708856

申请日：2019-12-10

Applicant: TOKYO ELECTRON LIMITED

Inventor： Akira KOSHIISHI ,  Masaru SUGIMOTO ,  Kunihiko HINATA ,  Noriyuki KOBAYASHI ,  Chishio KOSHIMIZU ,  Ryuji OHTANI ,  Kazuo KIBI ,  Masashi SAITO ,  Naoki MATSUMOTO ,  Yoshinobu OHYA ,  Manabu IWATA ,  Daisuke YANO ,  Yohei YAMAZAWA ,  Hidetoshi HANAOKA ,  Toshihiro HAYAMI ,  Hiroki YAMAZAKI ,  Manabu SATO

IPC: H01J37/32 ,  H01L21/67

Abstract: A plasma processing method includes executing an etching process that includes supplying an etching gas into a process container in which a target substrate is supported on a second electrode serving as a lower electrode, and applying an RF power for plasma generation and an RF power for ion attraction to turn the etching gas into plasma and to subject the target substrate to etching. The etching process includes applying a negative DC voltage to a first electrode serving as an upper electrode during the etching to increase an absolute value of self-bias on the first electrode. The etching process includes releasing DC electron current generated by the negative DC voltage to ground through plasma and a conductive member disposed as a ring around the first electrode, by using a first state where the conductive member is connected to a ground potential portion.

公开(公告)号：US20170032936A1

公开(公告)日：2017-02-02

申请号：US15290846

申请日：2016-10-11

Applicant: TOKYO ELECTRON LIMITED

Inventor： Akira KOSHIISHI ,  Masaru SUGIMOTO ,  Kunihiko HINATA ,  Noriyuki KOBAYASHI ,  Chishio KOSHIMIZU ,  Ryuji OHTANI ,  Kazuo KIBI ,  Masashi SAITO ,  Naoki MATSUMOTO ,  Manabu IWATA ,  Daisuke YANO ,  Yohei YAMAZAWA ,  Hidetoshi HANAOKA ,  Toshihiro HAYAMI ,  Hiroki YAMAZAKI ,  Manabu SATO

IPC: H01J37/32

CPC classification number: H01J37/32091 ,  H01J37/32082 ,  H01J37/32174 ,  H01J37/3244 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/3065

Abstract: An apparatus includes an upper electrode and a lower electrode for supporting a wafer disposed opposite each other within a process chamber. A first RF power supply configured to apply a first RF power having a relatively higher frequency, and a second RF power supply configured to apply a second RF power having a relatively lower frequency is connected to the lower electrode. A variable DC power supply is connected to the upper electrode. A process gas is supplied into the process chamber to generate plasma of the process gas so as to perform plasma etching.

Abstract translation: 一种装置包括用于支撑在处理室内相对设置的晶片的上电极和下电极。 被配置为施加具有相对较高频率的第一RF功率的第一RF电源和被配置为施加具有相对较低频率的第二RF功率的第二RF电源连接到下电极。 可变直流电源连接到上电极。 将工艺气体供应到处理室中以产生处理气体的等离子体，以进行等离子体蚀刻。

公开(公告)号：US20210082669A1

公开(公告)日：2021-03-18

申请号：US17105118

申请日：2020-11-25

Applicant: TOKYO ELECTRON LIMITED

Inventor： Akira KOSHIISHI ,  Masaru SUGIMOTO ,  Kunihiko HINATA ,  Noriyuki KOBAYASHI ,  Chishio KOSHIMIZU ,  Ryuji OHTANI ,  Kazuo KIBI ,  Masashi SAITO ,  Naoki MATSUMOTO ,  Yoshinobu OHYA ,  Manabu IWATA ,  Daisuke YANO ,  Yohei YAMAZAWA ,  Hidetoshi HANAOKA ,  Toshihiro HAYAMI ,  Hiroki YAMAZAKI ,  Manabu SATO

IPC: H01J37/32 ,  H01L21/67

Abstract: A plasma processing apparatus includes a process container that forms a process space to accommodate a target substrate, and a first electrode and a second electrode disposed opposite each other inside the process container. The first electrode is an upper electrode and the second electrode is a lower electrode and configured to support the target substrate through a mount face. A correction ring is disposed to surround the target substrate placed on the mount face of the second electrode. The correction ring includes a combination of a first ring to be around the target substrate and a second ring arranged around or above the first ring. A power supply unit is configured to apply a first electric potential and a second electric potential respectively to the first ring and the second ring to generate a potential difference between the first and second rings. The power supply unit is configured to variably set the potential difference.

公开(公告)号：US20140124139A1

公开(公告)日：2014-05-08

申请号：US14070190

申请日：2013-11-01

Applicant: TOKYO ELECTRON LIMITED

Inventor： Akira KOSHIISHI ,  Masaru SUGIMOTO ,  Kunihiko HINATA ,  Noriyuki KOBAYASHI ,  Chishio KOSHIMIZU ,  Ryuji OHTANI ,  Kazuo KIBI ,  Masashi SAITO ,  Naoki MATSUMOTO ,  Yoshinobu OHYA ,  Manabu IWATA ,  Daisuke YANO ,  Yohei YAMAZAWA ,  Hidetoshi HANAOKA ,  Toshihiro HAYAMI ,  Hiroki YAMAZAKI ,  Manabu SATO

IPC: H01J37/32

CPC classification number: H01J37/32422 ,  H01J37/32018 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32834 ,  H01J2237/2001 ,  H01J2237/334 ,  H01J2237/3344 ,  H01L21/67069 ,  Y10S156/915

Abstract: A plasma processing apparatus includes a first and second electrodes disposed on upper and lower sides and opposite each other within a process container, a first RF power application unit and a DC power supply both connected to the first electrode, and second and third radio frequency power application units both connected to the second electrode. A conductive member is disposed within the process container and grounded to release through plasma a current caused by a DC voltage applied from the DC power supply. The conductive member is supported by a first shield part around the second electrode and laterally protruding therefrom at a position between the mount face of the second electrode and an exhaust plate for the conductive member to be exposed to the plasma. The conductive member is grounded through a conductive internal body of the first shield part.

Abstract translation: 一种等离子体处理装置，包括在处理容器内设置在上侧和下侧并彼此相对的第一和第二电极，连接到第一电极的第一RF电力施加单元和DC电源，以及第二和第三射频功率 应用单元都连接到第二电极。 导电构件设置在处理容器内并接地以通过等离子体释放由直流电源施加的直流电压引起的电流。 导电构件由第二电极周围的第一屏蔽部分支撑，并且在第二电极的安装面和用于导电构件的排气板之间的位置处侧向突出以暴露于等离子体。 导电构件通过第一屏蔽部分的导电内部主体接地。

公开(公告)号：US20220013404A1

公开(公告)日：2022-01-13

申请号：US17448608

申请日：2021-09-23

Applicant: Tokyo Electron Limited

Inventor： Kazuo KIBI ,  Toshitake TSUDA ,  Kenji SUZUKI

IPC: H01L21/768 ,  H01L27/108

Abstract: A method for example manufacturing a semiconductor device, which includes: forming a hole in a region of an insulating film laminated on a substrate; embedding a first conductive material in the hole to a position lower than a height of a sidewall of the hole; further embedding a second conductive material through a selective growth in the hole in which the first conductive material has been embedded; and etching the second conductive material to form a contact pad at a position above the hole.

公开(公告)号：US20210384071A1

公开(公告)日：2021-12-09

申请号：US17445436

申请日：2021-08-19

Applicant: Tokyo Electron Limited

Inventor： Kazuo KIBI ,  Shigetsugu FUJITA ,  Kenji SUZUKI ,  Mitsuhiro OKADA

IPC: H01L21/768 ,  H01L21/027

Abstract: A method of manufacturing a semiconductor device includes: planarizing a surface of a substrate having a conductive material embedded in a first hole so as to expose the conductive material embedded in the first hole, wherein the first hole is formed in a region which is on an insulating film laminated on the substrate and is surrounded by a spacer film; laminating a mask film on the surface of the substrate; forming a second hole in the mask film such that at least a portion of an upper surface of the conductive material embedded in the first hole is exposed; embedding the conductive material in the second hole; and removing the mask film.

公开(公告)号：US20200381294A1

公开(公告)日：2020-12-03

申请号：US16996914

申请日：2020-08-19

Applicant: Tokyo Electron Limited

Inventor： Kazuo KIBI ,  Akihiro TAKAHASHI ,  Wataru SAKAMOTO

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/033

Abstract: There is formed, on a stack formed by alternately stacking an oxide film and a nitride film or an oxide film and a polysilicon film on a substrate, a hard mask in which two or more kinds of lines made of mutually different materials are arranged in order. Then, a photoresist is applied onto the hard mask. Furthermore, the photoresist is trimmed until one line is exposed from the end of the hard mask. Moreover, one line of the hard mask exposed beneath the photoresist is etched. Furthermore, a part of the stack exposed beneath the hard mask is etched. The etching of the photoresist, the hard mask, and the stack is repeated while changing etching conditions.