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    Semiconductor device having stacked chips
    1.
    发明授权
    Semiconductor device having stacked chips 有权

    公开(公告)号：US10985141B2

    公开(公告)日：2021-04-20

    申请号：US16726752

    申请日：2019-12-24

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Masaru Koyanagi

    IPC: H01L25/065 ,  H03K99/00 ,  G11C5/06 ,  G11C8/12 ,  H01L23/00 ,  G11C29/00 ,  G06F3/06 ,  G11C16/08 ,  H01L23/48 ,  H01L23/50 ,  G11C16/04

    Abstract: A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

    Non-volatile semiconductor storage device
    3.
    再颁专利
    Non-volatile semiconductor storage device 有权

    公开(公告)号：USRE47355E1

    公开(公告)日：2019-04-16

    申请号：US15649125

    申请日：2017-07-13

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

    IPC: G11C16/04 ,  G11C16/24

    Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10186487B2

    公开(公告)日：2019-01-22

    申请号：US15688848

    申请日：2017-08-28

    Applicant: Toshiba Memory Corporation

    Inventor： Kazushige Kawasaki ,  Mikihiko Ito ,  Masaru Koyanagi

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

    Abstract: A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.

    Semiconductor device having stacked chips
    5.
    发明授权
    Semiconductor device having stacked chips 有权

    公开(公告)号：US10157894B2

    公开(公告)日：2018-12-18

    申请号：US15819468

    申请日：2017-11-21

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Masaru Koyanagi

    IPC: H01L25/07 ,  H01L25/065 ,  H03K99/00 ,  G06F3/06 ,  G11C5/06 ,  G11C8/12 ,  G11C29/00 ,  G11C16/08 ,  H01L23/48 ,  H01L23/50 ,  G11C16/04 ,  H01L23/00

    Abstract: A semiconductor device includes a first chip having a first via and a second via through the first chip; and a second chip provided on the first chip and having a third via and a fourth via through the second chip. The first chip includes: a first logical operation circuit configured to perform a first logical operation (NOT) on a first address input signal to output a first address output signal to the second chip through the first via; a second logical operation circuit connected to the first logical operation circuit, the second logical operation circuit being configured to perform a second logical operation (XOR) on a second address input signal and the first address output signal to output a second address output signal to the second chip through the second via; and a first activation circuit connected to the second logical operation circuit, the first activation circuit being configured to activate the first chip based on at least the second address output signal.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10734360B2

    公开(公告)日：2020-08-04

    申请号：US16121171

    申请日：2018-09-04

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Satoshi Tsukiyama ,  Masaru Koyanagi ,  Mikihiko Ito ,  Kazushige Kawasaki

    IPC: H01L25/065 ,  H01L23/00

    Abstract: A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200014385A1

    公开(公告)日：2020-01-09

    申请号：US16571023

    申请日：2019-09-13

    Applicant: Toshiba Memory Corporation

    Inventor： Yasuhiro HIRASHIMA ,  Masaru Koyanagi ,  Yutaka Takayama

    IPC: H03K19/0175 ,  H01L23/538

    Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10461750B2

    公开(公告)日：2019-10-29

    申请号：US15907264

    申请日：2018-02-27

    Applicant: TOSHIBA MEMORY CORPORATION

    Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi ,  Yutaka Takayama

    IPC: G11C7/10 ,  H03K3/00 ,  H03K19/0175 ,  H01L23/538

    Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

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