公开(公告)号：US09786679B2

公开(公告)日：2017-10-10

申请号：US14844250

申请日：2015-09-03

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Mitsuhiro Omura

IPC: H01L27/115 ,  H01L27/112 ,  H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.

公开(公告)号：US10026622B2

公开(公告)日：2018-07-17

申请号：US15253827

申请日：2016-08-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Mitsuhiro Omura ,  Tsubasa Imamura ,  Itsuko Sakai

IPC: H01L21/311 ,  H01L27/115 ,  H01L21/67 ,  H01L21/3213

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a hole extending in a first direction in a workpiece. The method includes forming a first film on an upper surface of the workpiece and an upper portion of a side wall of the hole. The method includes forming a second film on the first film. The method includes removing portions of the first and second films from the upper surface of the workpiece so that at least a part of the first and second films formed on the upper portion remain. The method includes removing at least a part of a portion of the workpiece which is exposed through the hole using a second etchant. An etching rate of the first etchant for the first film is higher than an etching rate of the first etchant for the second film.

公开(公告)号：US09887093B1

公开(公告)日：2018-02-06

申请号：US15448552

申请日：2017-03-02

Applicant: Toshiba Memory Corporation

Inventor： Mitsuhiro Omura

IPC: H01L21/308 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/3085 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02282 ,  H01L21/0273 ,  H01L21/3081

Abstract: A semiconductor device manufacturing method includes forming a first resist and a second resist on a stacked body that includes a plurality of first films and a plurality of second films, the second resist facing one or more side surfaces of the first resist; forming a third film in a slit between the first resist and the second resist, the third film covering the side surfaces of the first resist and defining exposed surfaces of the first resist not covered by the third film; performing a first etch of the stacked body from an upper surface using the first resist, the second resist, and the third film as a mask; selectively etching the one or more exposed surfaces of the first resist and the second resist; and performing a second etch of the stacked body from the upper surface using the first resist and the third film as a mask.

公开(公告)号：US20170301691A1

公开(公告)日：2017-10-19

申请号：US15635398

申请日：2017-06-28

Applicant: Toshiba Memory Corporation

Inventor： Mitsuhiro Omura

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/522

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

公开(公告)号：US10153164B2

公开(公告)日：2018-12-11

申请号：US15661252

申请日：2017-07-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinichi Nakao ,  Shunsuke Ochiai ,  Yusuke Oshiki ,  Kei Watanabe ,  Mitsuhiro Omura

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. A hole or a groove is formed in the layer to be etched by performing dry etching on the layer to be etched using the patterned mask layer. The mask layer includes a first region and a second region. The first region includes boron and the second region includes boron such that a density of boron in the second region is different from a density of boron in the first region, or the first region includes carbon and the second region includes carbon such that a density of carbon in the second region is different from a density of carbon in the first region.

公开(公告)号：US09876022B1

公开(公告)日：2018-01-23

申请号：US15449689

申请日：2017-03-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomo Hasegawa ,  Kazuhisa Matsuda ,  Toshiyuki Sasaki ,  Mitsuhiro Omura

IPC: H01L21/311 ,  H01L27/11568 ,  H01L21/3065 ,  H01L21/027 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/0273 ,  H01L21/28282 ,  H01L21/3065

Abstract: A method for manufacturing a semiconductor device includes forming a resist film on a film to be processed. An upper portion of the film to be processed is processed using the resist film as a first mask. Tungsten or a tungsten compound is selectively formed on the resist film. A lower portion of the film to be processed is processed with a reducing gas using the tungsten or the tungsten compound as a second mask.

公开(公告)号：US09754793B2

公开(公告)日：2017-09-05

申请号：US15376336

申请日：2016-12-12

Applicant: Toshiba Memory Corporation

Inventor： Shinichi Nakao ,  Shunsuke Ochiai ,  Yusuke Oshiki ,  Kei Watanabe ,  Mitsuhiro Omura ,  Kosuke Horibe ,  Atsuko Sakata ,  Junichi Wada ,  Soichi Yamazaki ,  Masayuki Kitamura ,  Yuya Matsubara

IPC: H01L21/336 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11582

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11582 ,  H01L28/00

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.