公开(公告)号：US10930665B2

公开(公告)日：2021-02-23

申请号：US16536552

申请日：2019-08-09

Applicant: Toshiba Memory Corporation

Inventor： Kosuke Horibe ,  Kei Watanabe ,  Toshiyuki Sasaki ,  Tomo Hasegawa ,  Soichi Yamazaki ,  Keisuke Kikutani ,  Jun Nishimura ,  Hisashi Harada ,  Hideyuki Kinoshita

IPC: H01L27/11578 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

公开(公告)号：US20200091178A1

公开(公告)日：2020-03-19

申请号：US16291120

申请日：2019-03-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinichi Nakao ,  Kei Watanabe

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11565 ,  H01L29/40 ,  H01L23/00 ,  H01L21/02

Abstract: In one embodiment, a semiconductor device includes electrode layers and insulating layers alternately provided on a substrate and stacked in a first direction perpendicular to a surface of the substrate, and semiconductor layers provided in the electrode layers and insulating layers, extending in the first direction, and adjacent to each other in a second direction parallel to the surface of the substrate. The device further includes first and second charge trapping layers provided between the semiconductor layers and electrode layers sandwiching the semiconductor layers in a third direction parallel to the surface of the substrate. The device further includes insulators provided between the semiconductor layers being adjacent to each other in the second direction, and including a first insulator having a first width, and a second insulator having a second width longer than the first width and having nitrogen concentration different from that in the first insulator.

公开(公告)号：US20200235117A1

公开(公告)日：2020-07-23

申请号：US16536552

申请日：2019-08-09

Applicant: Toshiba Memory Corporation

Inventor： Kosuke HORIBE ,  Kei Watanabe ,  Toshiyuki Sasaki ,  Tomo Hasegawa ,  Soichi Yamazaki ,  Keisuke Kikutani ,  Jun Nishimura ,  Hisashi Harada ,  Hideyuki Kinoshita

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11565 ,  G11C16/04

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

公开(公告)号：US10566280B2

公开(公告)日：2020-02-18

申请号：US16103106

申请日：2018-08-14

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi Wakatsuki ,  Masayuki Kitamura ,  Takeshi Ishizaki ,  Hiroshi Itokawa ,  Daisuke Ikeno ,  Kei Watanabe ,  Atsuko Sakata

IPC: H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/532 ,  H01L21/28

Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.

公开(公告)号：US10937799B2

公开(公告)日：2021-03-02

申请号：US16291120

申请日：2019-03-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinichi Nakao ,  Kei Watanabe

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/11519 ,  H01L21/28 ,  H01L27/11556 ,  H01L21/02 ,  H01L27/11565 ,  H01L29/40 ,  H01L23/00 ,  H01L27/11568

Abstract: In one embodiment, a semiconductor device includes electrode layers and insulating layers alternately provided on a substrate and stacked in a first direction perpendicular to a surface of the substrate, and semiconductor layers provided in the electrode layers and insulating layers, extending in the first direction, and adjacent to each other in a second direction parallel to the surface of the substrate. The device further includes first and second charge trapping layers provided between the semiconductor layers and electrode layers sandwiching the semiconductor layers in a third direction parallel to the surface of the substrate. The device further includes insulators provided between the semiconductor layers being adjacent to each other in the second direction, and including a first insulator having a first width, and a second insulator having a second width longer than the first width and having nitrogen concentration different from that in the first insulator.

公开(公告)号：US09793293B1

公开(公告)日：2017-10-17

申请号：US15461509

申请日：2017-03-17

Applicant: Toshiba Memory Corporation

Inventor： Kosuke Horibe ,  Shinichi Nakao ,  Yasuhito Yoshimizu ,  Kouji Matsuo ,  Kei Watanabe ,  Atsuko Sakata

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/321 ,  H01L21/283

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/32105 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed; a columnar portion provided in the stacked body and extending in a stacking direction of the electrode layers; and a first separation region provided in the stacked body and extending in a first direction. The stacked body includes a memory cell array and a staircase portion arranged in the first direction, the memory cell array including memory cells provided along the columnar portion, and the staircase portion including a plurality of terraces arranged along the first direction. The first separation region includes a first portion and a second portion in the staircase portion, the first portion having a first width in a second direction crossing the first direction, and the second portion having a second width in the second direction. The second width is narrower than the first width.

公开(公告)号：US10541250B2

公开(公告)日：2020-01-21

申请号：US15195482

申请日：2016-06-28

Applicant: Toshiba Memory Corporation

Inventor： Ryohei Kitao ,  Atsuko Sakata ,  Takeshi Ishizaki ,  Satoshi Wakatsuki ,  Shinichi Nakao ,  Shunsuke Ochiai ,  Kei Watanabe

IPC: H01L27/00 ,  H01L27/11582 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

公开(公告)号：US10319734B2

公开(公告)日：2019-06-11

申请号：US15001991

申请日：2016-01-20

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito Yoshimizu ,  Akifumi Gawase ,  Kei Watanabe ,  Shinya Arai

IPC: H01L27/11582 ,  H01L21/764 ,  H01L23/532

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.

公开(公告)号：US10153164B2

公开(公告)日：2018-12-11

申请号：US15661252

申请日：2017-07-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinichi Nakao ,  Shunsuke Ochiai ,  Yusuke Oshiki ,  Kei Watanabe ,  Mitsuhiro Omura

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3065 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method for manufacturing a semiconductor device includes forming a mask layer including a) one metal from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium, b) boron, and c) carbon on a layer to be etched. The mask layer is patterned. A hole or a groove is formed in the layer to be etched by performing dry etching on the layer to be etched using the patterned mask layer. The mask layer includes a first region and a second region. The first region includes boron and the second region includes boron such that a density of boron in the second region is different from a density of boron in the first region, or the first region includes carbon and the second region includes carbon such that a density of carbon in the second region is different from a density of carbon in the first region.

公开(公告)号：US09905462B2

公开(公告)日：2018-02-27

申请号：US14985969

申请日：2015-12-31

Applicant: Toshiba Memory Corporation

Inventor： Atsuko Sakata ,  Takeshi Ishizaki ,  Shinya Okuda ,  Kei Watanabe ,  Masayuki Kitamura ,  Satoshi Wakatsuki ,  Daisuke Ikeno ,  Junichi Wada ,  Hirotaka Ogihara

IPC: H01L27/115 ,  H01L29/792 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/3065 ,  H01L29/788

CPC classification number: H01L21/76879 ,  H01L21/3065 ,  H01L21/76843 ,  H01L21/76864 ,  H01L27/11582 ,  H01L29/7881

Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.