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    Video disc locked groove corrector
    4.
    发明授权
    Video disc locked groove corrector 失效
    视频盘锁定凹槽校正器

    公开(公告)号：US4323998A

    公开(公告)日：1982-04-06

    申请号：US180389

    申请日：1980-08-21

    申请人： Kazuo Fukazawa ,  Akira Yamada

    发明人： Kazuo Fukazawa ,  Akira Yamada

    IPC分类号： G11B21/10 ,  G11B3/12 ,  G11B3/36 ,  G11B21/04 ,  G11B21/08

    CPC分类号： G11B21/04 ,  G11B21/085 ,  G11B3/127 ,  G11B3/36

    摘要： A video disc player having an adaptive bumper apparatus which tracks the signal pickup stylus to maintain a fixed spatial relation therebetween. The bumper is fixed to an electromechanical transducer secured to the stylus arm support carriage. Signals correlated to the relative disc-stylus velocity having frequency components of the once around rate of the disc are adapted to energize the transducer to cause the bumper to follow the motion of the stylus in the radial dimension. Disturbing visual effects resulting from disc defects, etc. which tend to kick the signal pickup stylus fore or aft of the current track position are significantly reduced.

    摘要翻译： 一种具有自适应保险杠装置的视频盘播放器，其跟踪信号拾取针笔以保持它们之间的固定的空间关系。 保险杠固定在固定在触笔支架上的机电换能器上。 与具有盘的一次绕射速率的频率分量相关联的相关圆盘笔迹速度的信号适于对换能器通电，以使保险杠沿径向尺寸跟随触针的运动。 由于光盘缺陷导致的令人不安的视觉效果显着降低，这些缺陷等倾向于使信号拾取针头在当前轨道位置的前面或后面。

    Line-locked clock signal generation system
    7.
    发明授权
    Line-locked clock signal generation system 失效
    线锁时钟信号发生系统

    公开(公告)号：US4791488A

    公开(公告)日：1988-12-13

    申请号：US84346

    申请日：1987-08-12

    申请人： Kazuo Fukazawa ,  Toshio Kaneuchi

    发明人： Kazuo Fukazawa ,  Toshio Kaneuchi

    IPC分类号： H03L7/06 ,  H03K5/00 ,  H03L7/183 ,  H04N5/04 ,  H04N5/12 ,  H04N5/907 ,  H04N5/932 ,  H04N9/804

    CPC分类号： H04N9/804 ,  H03L7/183 ,  H04N5/126 ,  H04N5/932

    摘要： A television receiver includes a phase-locked loop (PLL) which generates a clock signal having a frequency of N times the line frequency and being phase-locked to the horizontal line synchronizing signal. The clock signal produced by this PLL has a frequency which tends to jitter between N+1 and N-1 times the line frequency. To compensate for this jittering in the frequency of the clock signal, phase alignment circuitry is coupled to the PLL to align the phase of the clock signal to the horizontal drive signal produced by the PLL on the occurrence of each horizontal drive pulse. The PLL also includes a delay element which delays the horizontal drive signal applied to the phase comparator of the PLL. This delay element effectively advances the phase of the horizontal drive signal and the line-locked clock signal with respect to the horizontal sync signal to compensate for signal processing delays imparted in the generation of the horizontal drive signal and the clock signal.