-
公开(公告)号：US4912749A
公开(公告)日：1990-03-27
申请号：US149606
申请日：1988-01-28
IPC分类号： G11C17/00 , B42D15/02 , B42D15/10 , G03H1/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/10
摘要： In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.
-
公开(公告)号：US4870615A
公开(公告)日：1989-09-26
申请号：US150290
申请日：1988-01-29
IPC分类号： G11C17/00 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0433
摘要： A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.
-
公开(公告)号：US4930105A
公开(公告)日：1990-05-29
申请号：US178609
申请日：1988-04-07
申请人： Osamu Matsumoto , Tadashi Maruyama , Hiroyoshi Murata , Isao Abe , Tomohisa Shigematsu , Kazuyoshi Shinada , Yasoji Suzuki , Ichiro Kobayashi
发明人： Osamu Matsumoto , Tadashi Maruyama , Hiroyoshi Murata , Isao Abe , Tomohisa Shigematsu , Kazuyoshi Shinada , Yasoji Suzuki , Ichiro Kobayashi
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0416 , G11C16/0425
摘要： A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.
-
公开(公告)号：US4088958A
公开(公告)日：1978-05-09
申请号：US722761
申请日：1976-09-13
IPC分类号： G04G15/00 , G05B19/02 , G05B19/045 , G09G5/00 , G09G5/22 , H03J5/02 , H04B1/06 , H04N5/44 , H04B1/16
CPC分类号： H03J5/0245 , G04G15/006 , G05B19/045 , H04N5/45
摘要： An integrated circuit for a programmable television receiver comprises a memory for storing a plurality of programs, a digital clock and a character generating circuit for generating character signals for displaying the programs in the memory and/or time of the digital clock on the screen of a television receiver. The integrated circuit uses dynamic circuits to reduce the number of elements required, and CMOS transistors to attain a lower power dissipation.
摘要翻译： 一种用于可编程电视接收机的集成电路包括用于存储多个节目的存储器，数字时钟和字符产生电路，用于产生用于在存储器中显示节目的字符信号和/或数字时钟的时间在 电视接收机。 该集成电路使用动态电路来减少所需的元件数量，并使用CMOS晶体管来实现更低的功耗。
-
公开(公告)号：US3992635A
公开(公告)日：1976-11-16
申请号：US632575
申请日：1975-11-17
CPC分类号： H03K21/02
摘要： An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplied with pulses to be counted and each of the delay cicuits is set or reset to an initial state. There is also provided a closed loop circuit including a first gate circuit connected to receive an output signal from the last stage delay circuit as one input terminal, and a logic circuit connected to receive output signals from the first gate circuit and, for example, the first stage delay circuit and produce to the input terminal of the first stage delay circuit an output signal indicating coincidence or incoincidence of its input signals. The counter is capable of counting pulses of (2.sup.x -1) at maximum. A second gate circuit is provided to apply its output signal to the other input terminal of the first gate circuit and output signals of a predetermined combination from the unit delay circuits are supplied to the second gate circuit so that the counter can function as a counter with a counting capacity smaller than that of (2.sup.x -1).
摘要翻译： n比例计数器包括具有X个单元延迟电路的移位寄存器，它们串联连接，并且每个由多个绝缘栅场效应晶体管组成。 移位寄存器的单位延迟电路同时提供要计数的脉冲，并且每个延迟电路被设置或复位到初始状态。 还提供了一种闭环电路，包括连接成将来自最后级延迟电路的输出信号作为一个输入端子接收的第一门电路和连接成接收来自第一门电路的输出信号的逻辑电路，例如， 第一级延迟电路，并向第一级延迟电路的输入端产生指示其输入信号一致或不一致的输出信号。 计数器最多能够计数（2x-1）的脉冲。 提供第二门电路以将其输出信号施加到第一门电路的另一输入端，并且将来自单元延迟电路的预定组合的输出信号提供给第二门电路，使得计数器可用作具有 计数容量小于（2x-1）的计数容量。
-
公开(公告)号：US4143391A
公开(公告)日：1979-03-06
申请号：US917176
申请日：1978-06-20
申请人： Yasoji Suzuki , Tomohisa Shigematsu
发明人： Yasoji Suzuki , Tomohisa Shigematsu
IPC分类号： H01L27/092 , H01L27/02
CPC分类号： H01L27/0921
摘要： An integrated circuit device includes complementary MOS circuit elements formed in an N type semiconductor substrate with a P type region formed in the substrate. Protective circuit elements connected to an input terminal are formed in an area of the substrate other than the region thereof having the complementary MOS circuit elements formed therein. At least one of the regions constituting the protective circuit elements is formed in a P type additional region formed in the area of the N type substrate.
-
7.发明授权Configurable logic element with independently clocked outputs and node observation circuitry 失效具有独立时钟输出和节点观测电路的可配置逻辑元件
公开(公告)号：US5309045A
公开(公告)日：1994-05-03
申请号：US880591
申请日：1992-05-08
申请人： Yukihiro Saeki , Hiroki Muroga , Tomohisa Shigematsu , Toshio Hibi , Yasuo Kawahara , Kazunao Maru , Kenneth Austin , Gordon S. Work , Darren M. Wedgwood
发明人： Yukihiro Saeki , Hiroki Muroga , Tomohisa Shigematsu , Toshio Hibi , Yasuo Kawahara , Kazunao Maru , Kenneth Austin , Gordon S. Work , Darren M. Wedgwood
IPC分类号： G11C11/404 , G11C11/412 , H03K19/177 , H03K19/096
CPC分类号： H03K19/17764 , G11C11/404 , G11C11/412 , H03K19/17704 , H03K19/17728 , H03K19/1774
摘要： A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.
摘要翻译： 一种可编程逻辑单元电路，包括数据存储器电路，提供有至少两个输入信号的组合逻辑电路，基于数据存储电路中存储的数据的两个输入选择电路，选择提供给组合逻辑的两个输入信号 来自多于两个输入信号的电路，用于从组合逻辑电路提供与时钟信号同步的输出信号的时钟同步电路，以及用于选择组合的输出信号的3态输出型输出选择电路 逻辑电路或时钟同步电路的输出信号，这取决于数据存储电路中存储的数据。
-
8.发明授权Manufacturing method for a floating gate semiconductor memory device by forming cell slits 失效浮动栅极半导体存储器件的制造方法通过形成细胞片
公开(公告)号：US5219775A
公开(公告)日：1993-06-15
申请号：US836592
申请日：1992-02-18
申请人： Yukihiro Saeki , Osamu Matsumoto , Masayuki Yoshida , Takahide Mizutani , Nobuyoshi Chida , Tomohisa Shigematsu , Teruo Uemura , Kenji Toyoda , Hiroyuki Takamura
发明人： Yukihiro Saeki , Osamu Matsumoto , Masayuki Yoshida , Takahide Mizutani , Nobuyoshi Chida , Tomohisa Shigematsu , Teruo Uemura , Kenji Toyoda , Hiroyuki Takamura
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , Y10S148/106
摘要： A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.
-
公开(公告)号：US5214327A
公开(公告)日：1993-05-25
申请号：US577653
申请日：1990-09-04
IPC分类号： G06F7/00 , H03K3/037 , H03K3/356 , H03K17/041 , H03K17/693 , H03K19/177
CPC分类号： H03K19/1776 , H03K17/04106 , H03K17/693 , H03K19/17704 , H03K19/17736 , H03K19/1778 , H03K3/037 , H03K3/356147
摘要： A programmable logic device comprises a data storage circuit for storing 1-bit control data and a MOS transistor which is switch controlled in accordance with stored data in the data storage circuit. When the MOS transistor is switch controlled, the power supply voltage of the data storage circuit is raised. Two signal lines are connected with each other through the MOS transistor which has been rendered conductive, thereby permitting a signal to be transmitted between the signal lines.
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.023 秒)
