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公开(公告)号：US3992635A
公开(公告)日：1976-11-16
申请号：US632575
申请日：1975-11-17
CPC分类号： H03K21/02
摘要： An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplied with pulses to be counted and each of the delay cicuits is set or reset to an initial state. There is also provided a closed loop circuit including a first gate circuit connected to receive an output signal from the last stage delay circuit as one input terminal, and a logic circuit connected to receive output signals from the first gate circuit and, for example, the first stage delay circuit and produce to the input terminal of the first stage delay circuit an output signal indicating coincidence or incoincidence of its input signals. The counter is capable of counting pulses of (2.sup.x -1) at maximum. A second gate circuit is provided to apply its output signal to the other input terminal of the first gate circuit and output signals of a predetermined combination from the unit delay circuits are supplied to the second gate circuit so that the counter can function as a counter with a counting capacity smaller than that of (2.sup.x -1).
摘要翻译： n比例计数器包括具有X个单元延迟电路的移位寄存器，它们串联连接，并且每个由多个绝缘栅场效应晶体管组成。 移位寄存器的单位延迟电路同时提供要计数的脉冲，并且每个延迟电路被设置或复位到初始状态。 还提供了一种闭环电路，包括连接成将来自最后级延迟电路的输出信号作为一个输入端子接收的第一门电路和连接成接收来自第一门电路的输出信号的逻辑电路，例如， 第一级延迟电路，并向第一级延迟电路的输入端产生指示其输入信号一致或不一致的输出信号。 计数器最多能够计数（2x-1）的脉冲。 提供第二门电路以将其输出信号施加到第一门电路的另一输入端，并且将来自单元延迟电路的预定组合的输出信号提供给第二门电路，使得计数器可用作具有 计数容量小于（2x-1）的计数容量。
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2.发明授权Monolithic semiconductor mask programmable ROM and a method for manufacturing the same 失效单片半导体掩模可编程ROM及其制造方法
公开(公告)号：US4096522A
公开(公告)日：1978-06-20
申请号：US822657
申请日：1977-08-08
申请人： Yasoji Suzuki , Kenshi Manabe
发明人： Yasoji Suzuki , Kenshi Manabe
IPC分类号： G11C17/12 , H01L21/033 , H01L21/768 , H01L21/8246 , H01L23/522 , H01L27/112 , H01L29/78
CPC分类号： H01L27/11266 , G11C17/12 , H01L21/033 , H01L21/768 , H01L23/522 , H01L27/112 , H01L27/11233 , H01L2924/0002
摘要： A ROM with a matrix array of insulated gate enhancement type field effect transistors in each of which any information is not yet written is preliminarily prepared by a plurality of strip-shape diffusion regions doped at a predetermined interval in a given conductivity type semiconductor substrate and having a conductivity type opposite to that of the substrate, a plurality of strip-shape electroconductive metal layers formed through a first relatively thick insulation layer on the substrate at a predetermined interval so as to intersect the respective diffusion regions; and a plurality of gate electrode foils each formed through a second insulation layer thinner than the first insulation layer on that surface portion of the substrate which positions between the corresponding mutually facing ones of the diffusion regions so as integrally to project from the corresponding one of the electroconductive metal layers. An impression of information or absence thereof is controlled over the respective field effect transistors at the matrix intersections of the ROM by selectively implanting an impurity of the same conductivity type as that of the diffusion regions in the substrate through those exposed surface portions of the second insulation layer which are disposed between each of the gate electrode foils and the corresponding mutually facing ones of the diffusion regions, thereby providing an improved monolithic semiconductor mask programmable ROM and a method for manufacturing the same.
摘要翻译： 通过在给定的导电类型的半导体衬底中以预定的间隔掺杂的多个条状扩散区域，预先准备了其中尚未写入任何信息的绝缘栅极增强型场效应晶体管的矩阵阵列的ROM，并且具有 与基板相反的导电类型，多个条状导电金属层，以预定间隔以预定间隔穿过基板上的第一相对厚的绝缘层形成，以便与各个扩散区相交; 以及多个栅电极箔，每个栅极电极箔通过比基板的表面部分上的第一绝缘层更薄的第二绝缘层形成，所述第一绝缘层位于相应的相互面对的扩散区域之间，从而从相应的一个 导电金属层。 信息或不存在的印象通过在第二绝缘体的那些暴露表面部分选择性地注入与衬底中的扩散区相同的导电类型的杂质，在ROM的矩阵交叉点处的各个场效应晶体管上进行控制 层，其设置在每个栅电极箔和相应的相互面对的扩散区之间，从而提供改进的单片半导体掩模可编程ROM及其制造方法。
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3.发明授权Series logic circuit arrangement using a plurality of complementary IGFET's 失效使用多个互补IGFET（3s）的串联逻辑电路装置
公开(公告)号：US3945000A
公开(公告)日：1976-03-16
申请号：US493152
申请日：1974-07-30
申请人： Yasoji Suzuki , Kenshi Manabe
发明人： Yasoji Suzuki , Kenshi Manabe
IPC分类号： G11C17/00 , G11C17/12 , H01L21/822 , H01L27/04 , H01L27/112 , H03K19/00 , H03K19/0944 , H03K19/0948 , H03K19/177 , G08B5/36
CPC分类号： H03K19/1778 , H01L27/112 , H03K19/0948
摘要： A series logic circuit arrangement using a plurality of complementary IGFET's and comprising a plurality of series connected logic circuits, each of the logic circuits being designed to effect a predetermined logic function with respect to input binary coded signals by using at least one P channel IGFET and one N channel IFGET. In the negative logic system, the P channel IGFET's are arranged on a semiconductor substrate according to a logic equation of minterm-type expression, and the N channel IGFET's are arranged on the substrate according to a logic equation of maxterm-type expression, and, in the positive logic system, the N channel IGFET's are provided on the substrate according to the logic equation of minterm-type expression, and the P channel IGFET's are disposed on the substrate according to the logic equation of maxterm-type expression, thereby admitting of integrating the P and N channel IGFET's on the substrate within a smallest possible area.
摘要翻译： 一种使用多个互补IGFET并且包括多个串联连接的逻辑电路的串联逻辑电路装置，每个逻辑电路被设计成通过使用至少一个P沟道IGFET来实现关于输入二进制编码信号的预定逻辑功能，以及 一个N通道IFGET。 在负逻辑系统中，根据最小型表达式的逻辑方程将P沟道IGFET布置在半导体衬底上，并且根据maxterm型表达式的逻辑方程将N沟道IGFET排列在衬底上， 在正逻辑系统中，根据最小型表达式的逻辑方程，在衬底上提供N沟道IGFET，并且根据maxterm型表达式的逻辑方程将P沟道IGFET设置在衬底上，从而允许 在最小的可能区域内将P和N通道IGFET集成在衬底上。
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公开(公告)号：US4020362A
公开(公告)日：1977-04-26
申请号：US592643
申请日：1975-07-02
申请人： Yasoji Suzuki , Kenshi Manabe , Masataka Hirasawa
发明人： Yasoji Suzuki , Kenshi Manabe , Masataka Hirasawa
CPC分类号： G11C19/184 , H03K23/42 , H03K23/44
摘要： A counter comprises a cascade connection of an inverter stage and n one-bit shift register stages, the latter being operative in response to clock signals to be counted and each having a data-readin or front half-bit shift register stage and a data-readout or rear half-bit shift register stage. The output of the final stage in the cascade connection is coupled to the input of the first stage in the cascade connection. The output of the final stage is also coupled to an additional input of consecutive 1st to X-th shift register stages or consecutive 2nd to (X-1)-th shift register stages of an X-th shift register stage to constitute a scale-of-2n-X or 2n-(X-1) counter.
摘要翻译： 计数器包括逆变器级和n个1位移位寄存器级的级联连接，后者可响应于待计数的时钟信号而工作，每个具有数据读或前半位移位寄存器级和数据 - 读出或后半位移位寄存器级。 级联连接中的最后级的输出在级联连接中耦合到第一级的输入端。 最后级的输出还耦合到第X移位寄存器级的连续的第1至第X移位寄存器级或连续的第2至第（X-1）移位寄存器级的附加输入， 的2n-X或2n-（X-1）计数器。
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公开(公告)号：US4088958A
公开(公告)日：1978-05-09
申请号：US722761
申请日：1976-09-13
IPC分类号： G04G15/00 , G05B19/02 , G05B19/045 , G09G5/00 , G09G5/22 , H03J5/02 , H04B1/06 , H04N5/44 , H04B1/16
CPC分类号： H03J5/0245 , G04G15/006 , G05B19/045 , H04N5/45
摘要： An integrated circuit for a programmable television receiver comprises a memory for storing a plurality of programs, a digital clock and a character generating circuit for generating character signals for displaying the programs in the memory and/or time of the digital clock on the screen of a television receiver. The integrated circuit uses dynamic circuits to reduce the number of elements required, and CMOS transistors to attain a lower power dissipation.
摘要翻译： 一种用于可编程电视接收机的集成电路包括用于存储多个节目的存储器，数字时钟和字符产生电路，用于产生用于在存储器中显示节目的字符信号和/或数字时钟的时间在 电视接收机。 该集成电路使用动态电路来减少所需的元件数量，并使用CMOS晶体管来实现更低的功耗。
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公开(公告)号：US4930105A
公开(公告)日：1990-05-29
申请号：US178609
申请日：1988-04-07
申请人： Osamu Matsumoto , Tadashi Maruyama , Hiroyoshi Murata , Isao Abe , Tomohisa Shigematsu , Kazuyoshi Shinada , Yasoji Suzuki , Ichiro Kobayashi
发明人： Osamu Matsumoto , Tadashi Maruyama , Hiroyoshi Murata , Isao Abe , Tomohisa Shigematsu , Kazuyoshi Shinada , Yasoji Suzuki , Ichiro Kobayashi
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0416 , G11C16/0425
摘要： A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.
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公开(公告)号：US4912749A
公开(公告)日：1990-03-27
申请号：US149606
申请日：1988-01-28
IPC分类号： G11C17/00 , B42D15/02 , B42D15/10 , G03H1/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/10
摘要： In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.
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公开(公告)号：US4870615A
公开(公告)日：1989-09-26
申请号：US150290
申请日：1988-01-29
IPC分类号： G11C17/00 , G11C16/04 , H01L27/115
CPC分类号： H01L27/115 , G11C16/0433
摘要： A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.
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公开(公告)号：US4143391A
公开(公告)日：1979-03-06
申请号：US917176
申请日：1978-06-20
申请人： Yasoji Suzuki , Tomohisa Shigematsu
发明人： Yasoji Suzuki , Tomohisa Shigematsu
IPC分类号： H01L27/092 , H01L27/02
CPC分类号： H01L27/0921
摘要： An integrated circuit device includes complementary MOS circuit elements formed in an N type semiconductor substrate with a P type region formed in the substrate. Protective circuit elements connected to an input terminal are formed in an area of the substrate other than the region thereof having the complementary MOS circuit elements formed therein. At least one of the regions constituting the protective circuit elements is formed in a P type additional region formed in the area of the N type substrate.
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公开(公告)号：US3958187A
公开(公告)日：1976-05-18
申请号：US578985
申请日：1975-05-19
申请人： Yasoji Suzuki , Teruaki Tanaka
发明人： Yasoji Suzuki , Teruaki Tanaka
CPC分类号： H03K3/3545 , G04F5/06 , G04G3/02
摘要： Disclosed is a clock signal generating integrated circuit device comprising a quartz crystal oscillator section and a multistage frequency divider section. The crystal oscillator section and each frequency divider stage includes respectively complementary insulated gate field effect transistors. According to the present invention, the high frequency-operated field effect transistors have a lower threshold voltage than the remaining field effect transistors, so that the occupied area of the oscillator section can be decreased and simultaneously the power dissipation can also be reduced.
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