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    Integration film scheme for copper / low-k interconnect
    1.
    发明授权
    Integration film scheme for copper / low-k interconnect 有权
    铜/低k互连的集成电路方案

    公开(公告)号：US07244673B2

    公开(公告)日：2007-07-17

    申请号：US10706156

    申请日：2003-11-12

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    IPC分类号： H01L21/469

    CPC分类号： H01L23/53295 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer. The first, second and third low-dielectric constant materials sub-layers are preferably comprised of the same material, deposited continuously in one or more deposition chambers while the deposition conditions such as the gas flow rate, power, or gas species are adjusted or changed.

    摘要翻译： 用于多层互连层间介电层（ILD）的结构，其制造方法以及包括ILD层的半导体器件。 ILD层包括第一低介电常数材料子层和设置在第一低介电常数材料子层上的第二低介电常数材料子层。 第二低介电常数材料子层与第一低介电常数材料子层具有至少一种不同的材料特性。 第三低介电常数材料子层设置在第二低介电常数材料副层上，第三低介电常数材料子层与第二低介电常数材料子层具有至少一种不同的材料特性 -层。 第一，第二和第三低介电常数材料子层优选由相同的材料组成，其连续沉积在一个或多个沉积室中，同时调节或改变诸如气体流速，功率或气体种类的沉积条件 。

    Integration film scheme for copper / low-k interconnect
    2.
    发明申请
    Integration film scheme for copper / low-k interconnect 有权
    铜/低k互连的集成电路方案

    公开(公告)号：US20050098896A1

    公开(公告)日：2005-05-12

    申请号：US10706156

    申请日：2003-11-12

    申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Yih-Hsiung Lin ,  Tien-I Bao ,  Bi-Trong Chen ,  Yung-Cheng Lu

    IPC分类号： H01L23/532 ,  H01L23/48

    CPC分类号： H01L23/53295 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure for a multi-level interconnect inter-level dielectric layer (ILD), a method of manufacturing thereof, and a semiconductor device including the ILD layer. The ILD layer includes a first low-dielectric constant material sub-layer, and a second low-dielectric constant material sub-layer disposed over the first low-dielectric constant material sub-layer. The second low-dielectric constant material sub-layer has at least one different material property than the first low-dielectric constant material sub-layer. A third low-dielectric constant material sub-layer is disposed over the second low-dielectric constant material sub-layer, the third low-dielectric constant material sub-layer having at least one different material property than the second low-dielectric constant material sub-layer. The first, second and third low-dielectric constant materials sub-layers are preferably comprised of the same material, deposited continuously in one or more deposition chambers while the deposition conditions such as the gas flow rate, power, or gas species are adjusted or changed.

    摘要翻译： 用于多层互连层间介电层（ILD）的结构，其制造方法以及包括ILD层的半导体器件。 ILD层包括第一低介电常数材料子层和设置在第一低介电常数材料子层上的第二低介电常数材料子层。 第二低介电常数材料子层与第一低介电常数材料子层具有至少一种不同的材料特性。 第三低介电常数材料子层设置在第二低介电常数材料副层上，第三低介电常数材料子层与第二低介电常数材料子层具有至少一种不同的材料特性 -层。 第一，第二和第三低介电常数材料子层优选由相同的材料组成，其连续沉积在一个或多个沉积室中，同时调节或改变诸如气体流速，功率或气体种类的沉积条件 。

    Method of forming dummy copper plug to improve low k structure mechanical strength and plug fill uniformity
    3.
    发明授权
    Method of forming dummy copper plug to improve low k structure mechanical strength and plug fill uniformity 有权
    形成假铜塞以改善低k结构机械强度和塞填充均匀性的方法

    公开(公告)号：US06887790B1

    公开(公告)日：2005-05-03

    申请号：US10199856

    申请日：2002-07-19

    申请人： Tien-I Bao ,  Bi-Trong Chen ,  Ying-Ho Chen

    发明人： Tien-I Bao ,  Bi-Trong Chen ,  Ying-Ho Chen

    IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/522

    CPC分类号： H01L21/76838 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A new method is provided for the creation of dummy plugs in support of creating a robust structure of overlying interconnect traces. A pattern of holes for dummy plugs is etched stopping at an etch stop layer, the etch stop layer is then removed from the bottom of the holes that have been created whereby this removal is extended into an underlying layer of insulating material. The pattern of holes is filled with a metal, preferably copper, excess metal is removed by methods of Chemical Mechanical Polishing, leaving in place a pattern of metal plugs that penetrate through layers of insulation material and through layers of etch stop material and into an underlying layer of semiconductor material.

    摘要翻译： 提供了一种新的方法来创建虚拟插头，以支持创建上层互连线路的稳健结构。 在蚀刻停止层处蚀刻停止用于虚拟插头的孔的图案，然后从已经形成的孔的底部去除蚀刻停止层，由此将该去除延伸到下面的绝缘材料层中。 孔的图案填充有金属，优选铜，通过化学机械抛光的方法除去多余的金属，留下穿过绝缘材料层并通过蚀刻停止材料层的金属塞的图案，并进入下面的 半导体材料层。

    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
    4.
    发明授权
    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
    包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例

    公开(公告)号：US07723226B2

    公开(公告)日：2010-05-25

    申请号：US11654427

    申请日：2007-01-17

    申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

    摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

    Method for ultra low-K dielectric deposition
    5.
    发明申请
    Method for ultra low-K dielectric deposition 审中-公开
    超低K电介质沉积方法

    公开(公告)号：US20050048795A1

    公开(公告)日：2005-03-03

    申请号：US10649566

    申请日：2003-08-27

    申请人： Chung-Chi Ko ,  Yung-Cheng Lu ,  Tien-I Bao ,  Hui-Lin Chang ,  Syun-Ming Jang

    发明人： Chung-Chi Ko ,  Yung-Cheng Lu ,  Tien-I Bao ,  Hui-Lin Chang ,  Syun-Ming Jang

    IPC分类号： H01L21/312 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02271 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/7682

    摘要： The present invention provides a method of forming a semiconductor structure having an ultra low-K dielectric material that adheres well to the substrate. The method includes depositing a low-K material on the top surface of a substrate at a low temperature of no more than 250° by a CVD or spin-on process. The dielectric material is then cured by placing the substrate with the dielectric film in an environment where the temperature is regulated at about 400° or less as the dielectric film is being subjected to a plasma treatment or an E-beam treatment or UV treatment. The environment may further include one or more gases or a mixture of gases selected from the group consisting of H2, N2, NH3, CO2, all hydride gases and a mixture of these gases.

    摘要翻译： 本发明提供一种形成半导体结构的方法，所述半导体结构具有与基底良好粘合的超低K电介质材料。 该方法包括通过CVD或旋涂工艺在低于250°的低温下在衬底的顶表面上沉积低K材料。 然后通过将介质膜放置在介质膜经受等离子体处理或电子束处理或UV处理的温度调节在约400°或更小的环境中来固化电介质材料。 环境可以进一步包括选自H 2，N 2，NH 3，CO 2，所有氢化物气体和这些气体的混合物的一种或多种气体或气体混合物。

    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio
    7.
    发明申请
    Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio 有权
    包含双层多孔低k电介质的互连使用不同的致孔剂来构造前者的比例

    公开(公告)号：US20080171431A1

    公开(公告)日：2008-07-17

    申请号：US11654427

    申请日：2007-01-17

    申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

    摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

    Method for protecting sidewalls of etched openings to prevent via poisoning
    9.
    发明授权
    Method for protecting sidewalls of etched openings to prevent via poisoning 有权
    用于保护蚀刻开口的侧壁以防止通过中毒的方法

    公开(公告)号：US06602780B2

    公开(公告)日：2003-08-05

    申请号：US09947788

    申请日：2001-09-06

    申请人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

    发明人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

    IPC分类号： H01L214763

    CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L2221/1057

    摘要： A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.

    摘要翻译： 一种用于形成保护性氧化物衬垫以减少表面反射率的方法，包括在导电层上提供亲水性绝缘层; 在所述亲水绝缘层上提供抗反射涂层（ARC）层; 在抗反射涂层（ARC）层上提供蚀刻停止层; 在蚀刻停止层的表面上光刻地限定图案用于蚀刻; 各向异性蚀刻至少一个至少部分延伸穿过亲水性绝缘层的厚度的蚀刻开口; 沉积氧化物衬里，使得所述至少一个蚀刻开口和所述表面的侧壁和底部被所述氧化物衬垫覆盖; 并且根据化学机械（CMP）工艺将氧化物衬垫从辅助表面去除到表面反射率。