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    Method for ultra low-K dielectric deposition
    1.
    发明申请
    Method for ultra low-K dielectric deposition 审中-公开
    超低K电介质沉积方法

    公开(公告)号：US20050048795A1

    公开(公告)日：2005-03-03

    申请号：US10649566

    申请日：2003-08-27

    申请人： Chung-Chi Ko ,  Yung-Cheng Lu ,  Tien-I Bao ,  Hui-Lin Chang ,  Syun-Ming Jang

    发明人： Chung-Chi Ko ,  Yung-Cheng Lu ,  Tien-I Bao ,  Hui-Lin Chang ,  Syun-Ming Jang

    IPC分类号： H01L21/312 ,  H01L21/768 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02271 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/7682

    摘要： The present invention provides a method of forming a semiconductor structure having an ultra low-K dielectric material that adheres well to the substrate. The method includes depositing a low-K material on the top surface of a substrate at a low temperature of no more than 250° by a CVD or spin-on process. The dielectric material is then cured by placing the substrate with the dielectric film in an environment where the temperature is regulated at about 400° or less as the dielectric film is being subjected to a plasma treatment or an E-beam treatment or UV treatment. The environment may further include one or more gases or a mixture of gases selected from the group consisting of H2, N2, NH3, CO2, all hydride gases and a mixture of these gases.

    摘要翻译： 本发明提供一种形成半导体结构的方法，所述半导体结构具有与基底良好粘合的超低K电介质材料。 该方法包括通过CVD或旋涂工艺在低于250°的低温下在衬底的顶表面上沉积低K材料。 然后通过将介质膜放置在介质膜经受等离子体处理或电子束处理或UV处理的温度调节在约400°或更小的环境中来固化电介质材料。 环境可以进一步包括选自H 2，N 2，NH 3，CO 2，所有氢化物气体和这些气体的混合物的一种或多种气体或气体混合物。

    SiOCH low k surface protection layer formation by CxHy gas plasma treatment
    4.
    发明授权
    SiOCH low k surface protection layer formation by CxHy gas plasma treatment 有权
    SiOCH低k表面保护层通过CxHy气体等离子体处理形成

    公开(公告)号：US06962869B1

    公开(公告)日：2005-11-08

    申请号：US10270974

    申请日：2002-10-15

    申请人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

    发明人： Tien-I Bao ,  Hsin-Hsien Lu ,  Lih-Ping Li ,  Chung-Chi Ko ,  Aaron Song ,  Syun-Ming Jang

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/3105 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835

    摘要： A method of protecting a low k dielectric layer that is preferably comprised of a material containing Si, O, C, and H is described. The dielectric layer is subjected to a gas plasma that is generated from a CXHY gas which is preferably ethylene. Optionally, hydrogen may be added to the CXHY gas. Another alternative is a two step plasma process involving a first plasma treatment of CXHY or CXHY combined with H2 and a second plasma treatment with H2. The modified dielectric layer provides improved adhesion to anti-reflective layers and to a barrier metal layer in a damascene process. The modified dielectric layer also has a low CMP rate that prevents scratch defects and an oxide recess from occurring next to the metal layer on the surface of the damascene stack. The plasma treatments are preferably done in the same chamber in which the dielectric layer is deposited.

    摘要翻译： 描述了保护低k电介质层的方法，其优选由含有Si，O，C和H的材料组成。 对电介质层进行气化等离子体，该等离子体是由优选乙烯的C X H Y气产生的。 任选地，可以将氢气加入到C 1 H 2 H 2 O气体中。 另一种替代方案是涉及第一等离子体处理C X> Y Y or SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB >与H 2 H 2结合，并且与H 2 2进行第二等离子体处理。 改进的介电层在镶嵌工艺中提供对抗反射层和阻挡金属层的改善的粘合性。 改进的介电层也具有低CMP速率，其防止划痕缺陷和氧化物凹陷在镶嵌层的表面上邻近金属层发生。 等离子体处理优选在沉积介电层的相同的室中进行。

    Method for forming a carbon doped oxide low-k insulating layer
    5.
    发明授权
    Method for forming a carbon doped oxide low-k insulating layer 有权
    形成碳掺杂氧化物低k绝缘层的方法

    公开(公告)号：US06812043B2

    公开(公告)日：2004-11-02

    申请号：US10131713

    申请日：2002-04-25

    申请人： Tien-I Bao ,  Chung-Chi Ko ,  Lih-Ping Li ,  Syun-Ming Jang

    发明人： Tien-I Bao ,  Chung-Chi Ko ,  Lih-Ping Li ,  Syun-Ming Jang

    IPC分类号： H01L2100

    CPC分类号： H01L21/76826 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76807

    摘要： A method for forming a dielectric insulating layer with a reduced dielectric constant and increased hardness for semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing according to a CVD process a carbon doped oxide layer the CVD process including an oregano-silane precursor having Si—O groups and Si—Ry groups, where R is an alkyl or cyclo-alkyl group and y the number of R groups bonded to Si; and, exposing the carbon doped oxide layer to a hydrogen plasma treatment for a period of time thereby reducing the carbon doped oxide layer thickness including reducing the carbon doped oxide layer dielectric constant and increasing the carbon doped oxide layer hardness.

    摘要翻译： 一种用于半导体器件制造的具有降低的介电常数和增加的硬度的介电绝缘层的形成方法，包括提供具有在其上形成电介质绝缘层的工艺表面的半导体晶片; 根据CVD工艺沉积碳掺杂氧化物层的CVD工艺，其包括具有Si-O基团和Si-Ry基团的牛至硅烷前体，其中R是烷基或环烷基，y是与 硅; 并且将碳掺杂的氧化物层暴露于氢等离子体处理一段时间，从而减少碳掺杂的氧化物层厚度，包括减少碳掺杂的氧化物层介电常数并增加碳掺杂的氧化物层的硬度。

    Semiconductor devices with composite etch stop layers and methods of fabrication thereof
    7.
    发明授权
    Semiconductor devices with composite etch stop layers and methods of fabrication thereof 有权
    具有复合蚀刻停止层的半导体器件及其制造方法

    公开(公告)号：US07250364B2

    公开(公告)日：2007-07-31

    申请号：US10995923

    申请日：2004-11-22

    申请人： Yung-Cheng Lu ,  Tien-I Bao ,  Su-Hong Lin ,  Syun-Ming Jang

    发明人： Yung-Cheng Lu ,  Tien-I Bao ,  Su-Hong Lin ,  Syun-Ming Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76834

    摘要： Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially over the second etch stop layer, having a conductive layer therein down through the dielectric layer, the second etch stop layer and the first etch stop layer to the conductive member.

    摘要翻译： 具有复合蚀刻停止层的半导体器件及其制造方法。 具有复合蚀刻停止层的半导体器件包括具有导电部件的衬底，衬底上的第一蚀刻停止层和导电部件，在第二蚀刻停止层上顺序地具有第二蚀刻停止层和介电层，具有导电 在其中向下穿过介电层，第二蚀刻停止层和第一蚀刻停止层到达导电构件。

    Semiconductor devices with composite etch stop layers and methods of fabrication thereof
    8.
    发明申请
    Semiconductor devices with composite etch stop layers and methods of fabrication thereof 有权
    具有复合蚀刻停止层的半导体器件及其制造方法

    公开(公告)号：US20060110912A1

    公开(公告)日：2006-05-25

    申请号：US10995923

    申请日：2004-11-22

    申请人： Yung-Cheng Lu ,  Tien-I Bao ,  Su-Hong Lin ,  Syun-Ming Jang

    发明人： Yung-Cheng Lu ,  Tien-I Bao ,  Su-Hong Lin ,  Syun-Ming Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76834

    摘要： Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a second etch stop layer and a dielectric layer sequentially over the second etch stop layer, having a conductive layer therein down through the dielectric layer, the second etch stop layer and the first etch stop layer to the conductive member.

    摘要翻译： 具有复合蚀刻停止层的半导体器件及其制造方法。 具有复合蚀刻停止层的半导体器件包括具有导电部件的衬底，衬底上的第一蚀刻停止层和导电部件，在第二蚀刻停止层上顺序地具有第二蚀刻停止层和介电层，具有导电 在其中向下穿过介电层，第二蚀刻停止层和第一蚀刻停止层到达导电构件。