公开(公告)号：US11545619B2

公开(公告)日：2023-01-03

申请号：US16934341

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Hsiang Wang ,  Han-Ting Lin ,  Yu-Feng Yin ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Yin-Hao Wu ,  Kun-Yi Li ,  Meng-Chieh Wen ,  Lin-Ting Lin ,  Jiann-Horng Lin ,  An-Shen Chang ,  Huan-Just Lin

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.

公开(公告)号：US11626292B2

公开(公告)日：2023-04-11

申请号：US17195455

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chang Lee ,  Jiann-Horng Lin ,  Chih-Hao Chen ,  Ying-Hao Wu ,  Wen-Yen Chen ,  Shih-Hua Tseng ,  Shu-Huei Suen

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/02

Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.

公开(公告)号：US20230154760A1

公开(公告)日：2023-05-18

申请号：US18156123

申请日：2023-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiann-Horng Lin ,  Cheng-Li Fan ,  Chih-Hao Chen

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/76877 ,  H01L21/76807 ,  H01L21/32137 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/31138 ,  H01L21/32139

Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.

公开(公告)号：US10943791B2

公开(公告)日：2021-03-09

申请号：US16428029

申请日：2019-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chang Lee ,  Jiann-Horng Lin ,  Chih-Hao Chen ,  Ying-Hao Wu ,  Wen-Yen Chen ,  Shih-Hua Tseng ,  Shu-Huei Suen

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/02

Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.

公开(公告)号：US10276378B1

公开(公告)日：2019-04-30

申请号：US15797873

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Hao Wu ,  Chao-Kuei Yeh ,  Tai-Yen Peng ,  Yun-Yu Chen ,  Jiann-Horng Lin ,  Chih-Hao Chen

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.