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    4 port L-2L de-embedding method
    3.
    发明授权
    4 port L-2L de-embedding method 有权
    4端口L-2L去嵌入方式

    公开(公告)号：US09530705B2

    公开(公告)日：2016-12-27

    申请号：US13864376

    申请日：2013-04-17

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Chih-Yuan Chang ,  Min-Chie Jeng

    IPC: G01R31/27 ,  H01L21/66 ,  G01R31/26

    CPC classification number: H01L22/30 ,  G01R31/2607 ,  G01R31/27 ,  H01L22/34

    Abstract: Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first dummy component transmission lines operably couples a first signal test pad to a second signal test pad, and an other of the first dummy component transmission lines operably couples a third signal test pad to a fourth signal test pad. A second dummy component comprises two or more second dummy component transmission lines. One of the second dummy component transmission lines operably couples a fifth signal test pad to a sixth signal test pad, and an other of the second dummy component transmission lines operably couples a seventh signal test pad to an eighth signal test pad. Other embodiments are also disclosed.

    Abstract translation: 一些实施例涉及晶片。 该晶片包括包含两个或更多个第一虚拟部件传输线的第一虚拟部件。 第一虚拟部件传输线之一可操作地将第一信号测试焊盘耦合到第二信号测试焊盘，并且第一虚设部件传输线中的另一个可操作地将第三信号测试焊盘耦合到第四信号测试焊盘。 第二虚拟部件包括两个或更多个第二虚拟部件传输线。 第二虚拟部件传输线之一可操作地将第五信号测试焊盘耦合到第六信号测试焊盘，并且第二虚设部件传输线中的另一个可操作地将第七信号测试焊盘耦合到第八信号测试焊盘。 还公开了其他实施例。

    Transmission line for 3D integrated circuit
    4.
    发明授权
    Transmission line for 3D integrated circuit 有权
    三维集成电路传输线

    公开(公告)号：US09472513B2

    公开(公告)日：2016-10-18

    申请号：US14049516

    申请日：2013-10-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsiao-Tsung Yen

    IPC: H01P3/08 ,  H01L23/66

    CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01P3/08 ,  H01P3/082 ,  H01P3/088 ,  H01L2924/00

    Abstract: A semiconductor transmission line substructure and methods of transmitting RF signals are described. The semiconductor transmission line substructure can include a substrate; a first signal line over the substrate; a first ground line over the substrate; and a second semiconductor substrate over the substrate. The first signal line, the first ground line and the second semiconductor substrate are each vertically spaced apart from one another and can be separated from one another by at least one electrically insulating layer.

    Abstract translation: 描述了半导体传输线子结构和发射RF信号的方法。 半导体传输线子结构可以包括衬底; 衬底上的第一信号线; 衬底上的第一个接地线; 以及在所述衬底上的第二半导体衬底。 第一信号线，第一接地线和第二半导体衬底各自彼此垂直间隔开并且可以通过至少一个电绝缘层彼此分离。

    Voltage-controlled oscillator
    6.
    发明授权
    Voltage-controlled oscillator 有权
    压控振荡器

    公开(公告)号：US09425735B2

    公开(公告)日：2016-08-23

    申请号：US14701175

    申请日：2015-04-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ying-Ta Lu ,  Hsien-Yuan Liao ,  Chi-Hsien Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC: H03B5/12

    CPC classification number: H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1296

    Abstract: An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and a first, second, third, and fourth inductive elements. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The first and second inductive elements are electrically coupled to the first output nodes, respectively. The third inductive element is electrically coupled to one of the second output nodes and DC-biased and magnetically coupled to the first inductive element. The fourth inductive element is electrically coupled to the other of the second output nodes and DC-biased and magnetically coupled to the second inductive element.

    Abstract translation: 公开了一种装置，其包括第一交叉耦合晶体管对，第二交叉耦合晶体管对，至少一个电容单元以及第一，第二，第三和第四电感元件。 第一交叉耦合晶体管对和第二交叉耦合晶体管对分别耦合到一对第一输出节点和一对第二输出节点。 所述至少一个电容单元耦合到所述一对第一输出节点和所述一对第二输出节点中的至少一个。 第一和第二电感元件分别电耦合到第一输出节点。 第三感应元件电耦合到第二输出节点中的一个并被直流偏置并且磁耦合到第一电感元件。 第四电感元件电耦合到第二输出节点中的另一个并且被直流偏置并且磁耦合到第二电感元件。

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