公开(公告)号：US20190267211A1

公开(公告)日：2019-08-29

申请号：US16177530

申请日：2018-11-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC分类号： H01J37/32 ,  H01L21/02

摘要： Embodiments described herein relate to plasma processes. A tool includes a pedestal. The pedestal is configured to support a semiconductor substrate. The tool includes a bias source. The bias source is electrically coupled to the pedestal. The bias source is operable to bias the pedestal with a direct current (DC) voltage. The tool includes a plasma generator. The plasma generator is operable to generate a plasma remote from the pedestal. A method for semiconductor processing includes performing a plasma process on a substrate in a tool. The plasma process includes flowing a gas into the tool. The plasma process includes biasing a pedestal that supports the substrate in the tool. The plasma process includes igniting a plasma in the tool using the gas.

公开(公告)号：US20240071722A1

公开(公告)日：2024-02-29

申请号：US18504415

申请日：2023-11-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC分类号： H01J37/32 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321

CPC分类号： H01J37/32027 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32715 ,  H01L21/02063 ,  H01L21/0212 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31138 ,  H01L21/321 ,  H01J2237/3341

摘要： Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US11854766B2

公开(公告)日：2023-12-26

申请号：US17869557

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Liang Pan ,  Bing-Hung Chen ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang ,  Jack Kuo-Ping Kuo

IPC分类号： H01L21/321 ,  H01L21/311 ,  H01J37/32 ,  H01L21/02

CPC分类号： H01J37/32027 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32715 ,  H01L21/0212 ,  H01L21/02063 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31138 ,  H01L21/321 ,  H01J2237/3341

摘要： Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

公开(公告)号：US20230343636A1

公开(公告)日：2023-10-26

申请号：US18344229

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/263 ,  H01L21/311

CPC分类号： H01L21/76802 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/2633 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76877

摘要： A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US10943791B2

公开(公告)日：2021-03-09

申请号：US16428029

申请日：2019-05-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Chang Lee ,  Jiann-Horng Lin ,  Chih-Hao Chen ,  Ying-Hao Wu ,  Wen-Yen Chen ,  Shih-Hua Tseng ,  Shu-Huei Suen

IPC分类号： H01L21/311 ,  H01L21/027 ,  H01L21/02

摘要： In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.

公开(公告)号：US09484207B2

公开(公告)日：2016-11-01

申请号：US14292167

申请日：2014-05-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Jeng-Chang Her ,  Chia-Cheng Lin ,  Hung-Jui Chang ,  Yu-Sheng Su ,  Shu-Huei Suen

IPC分类号： H01L21/768 ,  H01L21/285

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.

摘要翻译： 提供一种形成半导体器件结构的方法。 该方法包括提供具有中心部分和围绕中心部分的周边部分的晶片。 该方法包括在中心部分上形成第一介电层。 第一电介质层具有暴露晶片的导电区域的第一接触开口。 该方法包括在周边部分上形成保护层。 该方法包括在形成保护层之后，执行金属硅化物工艺以在晶片的导电区域上形成金属硅化物结构。

公开(公告)号：US11735469B2

公开(公告)日：2023-08-22

申请号：US17661600

申请日：2022-05-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/768 ,  H01L21/02 ,  H01L21/263 ,  H01L21/311

CPC分类号： H01L21/76802 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/2633 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76877

摘要： A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US11322393B2

公开(公告)日：2022-05-03

申请号：US17120989

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/263

摘要： A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US20210134657A1

公开(公告)日：2021-05-06

申请号：US17120989

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/263

摘要： A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US10755945B2

公开(公告)日：2020-08-25

申请号：US16035819

申请日：2018-07-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pang-Sheng Chang ,  Yu-Feng Yin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao ,  Chia-Yang Hung ,  Chia-Sheng Chang ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Sheng-Liang Pan ,  Jack Kuo-Ping Kuo ,  Shao-Jyun Wu

IPC分类号： H01L21/321 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

摘要： A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.