公开(公告)号：US20240079315A1

公开(公告)日：2024-03-07

申请号：US17901442

申请日：2022-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Shin WANG ,  Yu-Hsiang Wang ,  Wei-Ting Chang ,  Fan-Yi Hsu

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L29/40

CPC classification number: H01L23/5226 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/53257 ,  H01L29/401

Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.

公开(公告)号：US20240258387A1

公开(公告)日：2024-08-01

申请号：US18314446

申请日：2023-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Syuan Siao ,  Meng-Han Chou ,  Chien-Yu Lin ,  Wei-Ting Chang ,  Tien-Shun Chang ,  Chin-I Kuan ,  Su-Hao Liu ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.

公开(公告)号：US11121230B2

公开(公告)日：2021-09-14

申请号：US16575668

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chen ,  Wei-Ting Chang ,  Yu-Shine Lin ,  Jiang-He Xie

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/207 ,  H01L29/10 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

公开(公告)号：US11843042B2

公开(公告)日：2023-12-12

申请号：US17405922

申请日：2021-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chen ,  Wei-Ting Chang ,  Yu-Shine Lin ,  Jiang-He Xie

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/207 ,  H01L29/10 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/02579 ,  H01L29/10 ,  H01L29/207 ,  H01L29/7787 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/205

Abstract: Structures and methods for controlling dopant diffusion and activation are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a channel layer; a barrier layer over the channel layer; a gate electrode over the barrier layer; and a doped layer formed between the barrier layer and the gate electrode. The doped layer includes (a) an interface layer in contact with the barrier layer and (b) a main layer between the interface layer and the gate electrode. The doped layer comprises a dopant whose doping concentration in the interface layer is lower than that in the main layer.

公开(公告)号：US20230008413A1

公开(公告)日：2023-01-12

申请号：US17651251

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Kang Ho ,  Kuo-Ju Chen ,  Wei-Ting Chang ,  Wei-Fu Wang ,  Li-Ting Wang ,  Huicheng Chang ,  Yee-Chia Yeo ,  Yi-Chao Wang ,  Tsai-Yu Huang

IPC: H01L29/66

Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; and forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.