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公开(公告)号：US11209878B2
公开(公告)日：2021-12-28
申请号：US16441637
申请日：2019-06-14
摘要： In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.
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公开(公告)号：US20220091646A1
公开(公告)日：2022-03-24
申请号：US17543542
申请日：2021-12-06
摘要： In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.
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3.发明申请STRUCTURE AND METHOD TO MITIGATE SOLDERING OFFSET FOR WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) APPLICATIONS 审中-公开用于降低水平芯片尺寸封装（WLCSP）应用的焊接偏移的结构和方法公开(公告)号：US20160264402A1
公开(公告)日：2016-09-15
申请号：US14645650
申请日：2015-03-12
发明人： Shao-Chi Yu , Chia-Ming Hung , Hsin-Ting Huang , Hsiang-Fu Chen , Allen Timothy Chang , Wen-Chuan Tai
CPC分类号： B81C1/0023 , B81B7/0048 , B81B7/0051 , B81B7/0054 , B81B7/007 , H01L2224/04026 , H01L2224/05624 , H01L2224/05644 , H01L2224/16225 , H01L2224/2957 , H01L2224/29624 , H01L2224/29644
摘要： The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.
摘要翻译： 本公开涉及一种具有应力吸收帽基片的晶片级芯片级封装（WLCSP）。 盖基板通过结合环和布置在盖基板的上表面上的接合焊盘接合到管芯。 贯穿衬底通孔（TSV）从接合焊盘延伸穿过盖衬底到帽衬底的下表面。 此外，上表面中的凹槽围绕接合焊盘延伸并且沿着接合环的侧壁延伸。 凹槽吸收诱发的应力，从而减轻模具中的任何装置偏移。
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公开(公告)号：US11360045B2
公开(公告)日：2022-06-14
申请号：US16441672
申请日：2019-06-14
IPC分类号： G01N27/414 , B01L3/00
摘要： In an embodiment, a device includes: an electrode configured to change a contact angle of a liquid droplet above the electrode when a first voltage is applied to the electrode; a sensing film overlaying the electrode, wherein the electrode is configured for assessment of a state of the liquid droplet based on a second voltage sensed at the electrode; a reference electrode above the electrode, the reference electrode configured to provide a reference voltage; and a microfluidic channel between the electrode and the reference electrode, wherein the microfluidic channel is configured to manipulate the liquid droplet using the electrode.
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公开(公告)号：US20160341656A1
公开(公告)日：2016-11-24
申请号：US14719991
申请日：2015-05-22
发明人： Yi-Shao Liu , Emerson Cheng , Yi-Hsien Chang , Chun-Ren Cheng , Ching-Ray Chen , Alex Kalnitsky , Allen Timothy Chang
IPC分类号： G01N21/03 , H01L27/146 , G01N21/64
CPC分类号： B01L3/50 , B01L3/502715 , B01L2300/0636 , B01L2300/0645 , B01L2300/0654 , B01L2300/0816 , B01L2300/0887 , B01L2300/168 , B01L2300/1827 , B01L2400/0424 , G01N21/6428 , G01N21/6454 , G01N21/648 , G01N27/414 , G01N2021/6482 , H01L27/1203 , H01L27/1211
摘要： The present disclosure relates to an integrated chip having an integrated optical bio-sensor, and an associated method of fabrication. In some embodiments, the integrated optical bio-sensor has a sensing device arranged within a semiconductor substrate. An optical waveguide structure is located over a first side of the semiconductor substrate at a position over the sensing device. A dielectric structure is disposed onto the optical waveguide structure at a position that separates the optical waveguide structure from a sample retention area configured to receive a sample solution.
摘要翻译： 本公开涉及具有集成光学生物传感器的集成芯片以及相关联的制造方法。 在一些实施例中，集成光学生物传感器具有布置在半导体衬底内的感测装置。 光学波导结构位于半导体衬底的位于传感器件上方的位置的第一侧上。 在将光波导结构与被配置为接收样品溶液的样品保留区域分离的位置处设置在光波导结构上的电介质结构。
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6.发明申请公开(公告)号：US20160130137A1
公开(公告)日：2016-05-12
申请号：US14557513
申请日：2014-12-02
发明人： Hsin-Ting Huang , Hsiang-Fu Chen , Wen-Chuan Tai , Shao-Chi Yu , Chia-Ming Hung , Allen Timothy Chang , Bruce C.S. Chou , Chin-Min Lin
CPC分类号： B81C1/00285 , B81B7/02 , B81B2201/0235 , B81B2201/0242 , B81B2207/095 , B81B2207/096 , B81C2203/0145
摘要： Some embodiments relate to multiple MEMS devices that are integrated together on a single substrate. A device substrate comprising first and second micro-electro mechanical system (MEMS) devices is bonded to a capping structure. The capping structure comprises a first cavity arranged over the first MEMS device and a second cavity arranged over the second MEMS device. The first cavity is filled with a first gas at a first gas pressure. The second cavity is filled with a second gas at a second gas pressure, which is different from the first gas pressure. A recess is arranged within a lower surface of the capping structure. The recess abuts the second cavity. A vent is arranged within the capping structure. The vent extends from a top of the recess to the upper surface of the capping structure. A lid is arranged within the vent and configured to seal the second cavity.
摘要翻译： 一些实施例涉及在单个基板上集成在一起的多个MEMS器件。 包括第一和第二微机电系统（MEMS）装置的装置基板被结合到封盖结构。 封盖结构包括布置在第一MEMS器件上的第一腔和布置在第二MEMS器件上的第二腔。 第一腔体以第一气体压力填充第一气体。 第二腔体以与第一气体压力不同的第二气体压力填充第二气体。 凹口布置在封盖结构的下表面内。 凹槽邻接第二腔。 在封盖结构内设有排气口。 通气孔从凹槽的顶部延伸到封盖结构的上表面。 盖子布置在通气口内并构造成密封第二腔体。
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公开(公告)号：US11747299B2
公开(公告)日：2023-09-05
申请号：US17826882
申请日：2022-05-27
IPC分类号： G01N27/414 , B01L3/00
CPC分类号： G01N27/4145 , B01L3/502715 , B01L2200/06 , B01L2300/0645 , B01L2400/0415
摘要： In an embodiment, a device includes: an electrode configured to change a contact angle of a liquid droplet above the electrode when a first voltage is applied to the electrode; a sensing film overlaying the electrode, wherein the electrode is configured for assessment of a state of the liquid droplet based on a second voltage sensed at the electrode; a reference electrode above the electrode, the reference electrode configured to provide a reference voltage; and a microfluidic channel between the electrode and the reference electrode, wherein the microfluidic channel is configured to manipulate the liquid droplet using the electrode.
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公开(公告)号：US20220299468A1
公开(公告)日：2022-09-22
申请号：US17826882
申请日：2022-05-27
IPC分类号： G01N27/414 , B01L3/00
摘要： In an embodiment, a device includes: an electrode configured to change a contact angle of a liquid droplet above the electrode when a first voltage is applied to the electrode; a sensing film overlaying the electrode, wherein the electrode is configured for assessment of a state of the liquid droplet based on a second voltage sensed at the electrode; a reference electrode above the electrode, the reference electrode configured to provide a reference voltage; and a microfluidic channel between the electrode and the reference electrode, wherein the microfluidic channel is configured to manipulate the liquid droplet using the electrode.
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公开(公告)号：US10131540B2
公开(公告)日：2018-11-20
申请号：US14645650
申请日：2015-03-12
发明人： Shao-Chi Yu , Chia-Ming Hung , Hsin-Ting Huang , Hsiang-Fu Chen , Allen Timothy Chang , Wen-Chuan Tai
摘要： The present disclosure relates to a wafer level chip scale package (WLCSP) with a stress absorbing cap substrate. The cap substrate is bonded to a die through a bond ring and a bond pad arranged on an upper surface of the cap substrate. A through substrate via (TSV) extends from the bond pad, through the cap substrate, to a lower surface of the cap substrate. Further, recesses in the upper surface extend around the bond pad and along sidewalls of the bond ring. The recesses absorb induced stress, thereby mitigating any device offset in the die.
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公开(公告)号：US09968927B2
公开(公告)日：2018-05-15
申请号：US14719991
申请日：2015-05-22
发明人： Yi-Shao Liu , Emerson Cheng , Yi-Hsien Chang , Chun-Ren Cheng , Ching-Ray Chen , Alex Kalnitsky , Allen Timothy Chang
IPC分类号： H01L27/12 , G01N27/414 , G01N21/64 , B01L3/00
CPC分类号： B01L3/50 , B01L3/502715 , B01L2300/0636 , B01L2300/0645 , B01L2300/0654 , B01L2300/0816 , B01L2300/0887 , B01L2300/168 , B01L2300/1827 , B01L2400/0424 , G01N21/6428 , G01N21/6454 , G01N21/648 , G01N27/414 , G01N2021/6482 , H01L27/1203 , H01L27/1211
摘要： The present disclosure relates to an integrated chip having an integrated optical bio-sensor, and an associated method of fabrication. In some embodiments, the integrated optical bio-sensor has a sensing device arranged within a semiconductor substrate. An optical waveguide structure is located over a first side of the semiconductor substrate at a position over the sensing device. A dielectric structure is disposed onto the optical waveguide structure at a position that separates the optical waveguide structure from a sample retention area configured to receive a sample solution.
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