公开(公告)号：US20180061987A1

公开(公告)日：2018-03-01

申请号：US15804887

申请日：2017-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： I-Chih CHEN ,  Ying-Lang WANG ,  Chih-Mu HUANG ,  Ying-Hao CHEN ,  Wen-Chang KUO ,  Jung-Chi JENG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165

Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.

公开(公告)号：US20170317164A1

公开(公告)日：2017-11-02

申请号：US15651751

申请日：2017-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih CHEN ,  Chih-Mu HUANG ,  Fu-Tsun TSAI ,  Meng-Yi WU ,  Yung-Fa LEE ,  Ying-Lang WANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/0638 ,  H01L21/26506 ,  H01L29/0603 ,  H01L29/0847 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

公开(公告)号：US20170352574A1

公开(公告)日：2017-12-07

申请号：US15171806

申请日：2016-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kei-Wei CHEN ,  Chun-Hsiung TSAI ,  Huai-Tei YANG ,  Shiu-Ko JANGJIAN ,  Ying-Lang WANG ,  Ziwei FANG

IPC: H01L21/687 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/67

CPC classification number: H01L21/68764 ,  H01J37/32082 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/3065

Abstract: An apparatus for treating a wafer is provided. The apparatus includes a platen, a chamber, an etch gas supplier and a tilting mechanism. The chamber has at least one aperture at least partially facing to the platen. The etch gas supplier is fluidly connected to the chamber. The tilting mechanism is coupled with the platen for allowing the platen to have at least one first degree of freedom to tilt relative to the aperture of the chamber.

公开(公告)号：US20170033179A1

公开(公告)日：2017-02-02

申请号：US14812864

申请日：2015-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming LIN ,  Shiu-Ko JANGJIAN ,  Chun-Che LIN ,  Ying-Lang WANG ,  Wei-Ken LIN ,  Chuan-Pu LIU

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/3105 ,  H01L27/088 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

Abstract translation: 半导体器件的沟槽结构包括衬底，隔离结构和衬里层。 衬底在其中具有沟槽。 隔离结构设置在沟槽中。 衬垫层设置在衬底和隔离结构之间。 衬里层包括氮气，衬层具有空间上各种氮浓度。

公开(公告)号：US20130320541A1

公开(公告)日：2013-12-05

申请号：US13961908

申请日：2013-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh CHANG ,  Chih-Chung CHANG ,  Kei-Wei CHEN ,  Ying-Lang WANG

IPC: H01L23/532

CPC classification number: H01L23/53266 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor contact structures extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.

Abstract translation: 半导体接触结构延伸穿过电介质材料并且提供与包括硅化物材料和非硅化物材料（例如掺杂硅）的多个不同的下层材料的接触。 接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。 下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。 复合层可以由钛形成。 在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。 诸如钨或铜的导电插塞材料填充接触开口。

公开(公告)号：US20210083048A1

公开(公告)日：2021-03-18

申请号：US17107448

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming LIN ,  Shiu-Ko JANGJIAN ,  Chun-Che LIN ,  Ying-Lang WANG ,  Wei-Ken LIN ,  Chuan-Pu LIU

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

Abstract: A structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The isolation structure is embedded in the substrate. The isolation structure has a bottom surface and a sidewall. The liner layer is between the substrate and the isolation. A first portion of the liner layer in contact with the sidewall of the isolation structure has a nitrogen concentration lower than a second portion of the liner layer in contact with the bottom surface of the isolation structure.

公开(公告)号：US20180281152A1

公开(公告)日：2018-10-04

申请号：US15646414

申请日：2017-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kei-Wei CHEN ,  Chih-Hung CHEN ,  Ying-Lang WANG

IPC: B24B57/02 ,  B24B37/04 ,  B24B37/013

Abstract: A slurry dispensing unit for a chemical mechanical polishing (CMP) apparatus is provided. The slurry dispensing unit includes a nozzle, a mixer, a first fluid source, and a second fluid source. The nozzle is configured to dispense a slurry. The mixer is disposed upstream of the nozzle. The first fluid source is connected to the mixer through a first pipe and configured to provide a first fluid including a first component of the slurry. The second fluid source is connected to the mixer through a second pipe and configured to provide a second fluid including a second component of the slurry, wherein the second component is different from the first component.

公开(公告)号：US20180151667A1

公开(公告)日：2018-05-31

申请号：US15865072

申请日：2018-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming LIN ,  Shiu-Ko JANGJIAN ,  Chun-Che LIN ,  Ying-Lang WANG ,  Wei-Ken LIN ,  Chuan-Pu LIU

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/785

Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.

公开(公告)号：US20160114460A1

公开(公告)日：2016-04-28

申请号：US14987843

申请日：2016-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Chang CHAO ,  Kei-Wei CHEN ,  Ying-Lang WANG

IPC: B24B53/12

CPC classification number: B24B53/12 ,  B24B53/017 ,  B24D3/06 ,  B24D3/28 ,  B24D18/00

Abstract: A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process.

公开(公告)号：US20140167199A1

公开(公告)日：2014-06-19

申请号：US13717883

申请日：2012-12-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Pin CHENG ,  Jung-Liang CHIEN ,  Chih-Kang CHAO ,  Chi-Cherng JENG ,  Hsin-Chi CHEN ,  Ying-Lang WANG

IPC: H01L23/544

CPC classification number: H01L21/78 ,  H01L22/32 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/00

Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.

Abstract translation: 一种半导体晶片，具有排列在阵列中的晶片上的多个芯片晶粒区域，每个芯片晶粒区域包括具有一个或多个第一组多边形结构的密封环区域。 晶片还包括在芯片模具区域之间的划线区域，划线区域包括一个或多个第二组多边形结构。 切割线和密封环区域之间的近似多边形结构的存在在晶片切割操作期间平衡芯片晶片区域之间的应力。