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    Integrated Circuit Layouts with Fill Feature Shapes
    3.
    发明申请
    Integrated Circuit Layouts with Fill Feature Shapes 审中-公开

    公开(公告)号：US20190005180A1

    公开(公告)日：2019-01-03

    申请号：US15637484

    申请日：2017-06-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Cheng Yeh ,  Yen-Sen Wang ,  Ming-Yi Lin

    IPC: G06F17/50

    Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.

    PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT
    4.
    发明申请
    PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT 有权
    用于断电电压改进的功率器件的部分SOI

    公开(公告)号：US20140322871A1

    公开(公告)日：2014-10-30

    申请号：US14330092

    申请日：2014-07-14

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Long-Shih Lin ,  Fu-Hsiung Yang ,  Kun-Ming Huang ,  Ming-Yi Lin ,  Paul Chu

    IPC: H01L29/66 ,  H01L21/308

    CPC classification number: H01L21/308 ,  G01R31/129 ,  G01R31/2637 ,  H01L21/3083 ,  H01L21/76275 ,  H01L21/76283 ,  H01L29/086 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7394 ,  H01L29/7824

    Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

    Abstract translation: 本公开的一些实施例涉及增加功率器件的击穿电压的方法。 功率器件形成在由器件晶片，手柄晶片和中间氧化物层构成的绝缘体上硅（SOI）晶片上。 在处理晶片的下表面上形成凹口，以限定处理晶片的凹陷区域。 处理晶片的凹陷区域具有大于零的第一处理晶片厚度。 处理晶片的未凹陷区域具有大于第一处理晶片厚度的第二处理晶片厚度。 凹陷区域的第一处理晶片厚度为功率器件提供了击穿电压的改善。

    Cut mask design layers to provide compact cell height
    5.
    发明授权
    Cut mask design layers to provide compact cell height 有权
    切割面膜设计层以提供紧凑的细胞高度

    公开(公告)号：US09551923B2

    公开(公告)日：2017-01-24

    申请号：US14247409

    申请日：2014-04-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Sen Wang ,  Ming-Yi Lin ,  Chen-Hung Lu ,  Jyh-Kang Ting

    IPC: G06F17/50 ,  G03F1/00

    CPC classification number: G03F1/00 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

    Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

    Abstract translation: 一些实施例涉及设计集成电路布局的方法。 在该方法中，在布局的图形表示内的有效区域上，在不同的设计层上提供多个设计形状。 连接在形成在第一设计层上的第一设计形状和形成在第一设计层上的第二设计形状之间垂直延伸。 产生分别在第一和第二切割掩模设计层上的第一和第二切割掩模形状。 第一切割形状去除第一设计层的部分，并且第二切割形状去除第二设计层的部分。

    Integrated Circuit Layouts with Fill Feature Shapes
    7.
    发明申请
    Integrated Circuit Layouts with Fill Feature Shapes 有权

    公开(公告)号：US20220277128A1

    公开(公告)日：2022-09-01

    申请号：US17745224

    申请日：2022-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Cheng Yeh ,  Yen-Sen Wang ,  Ming-Yi Lin

    IPC: G06F30/392 ,  G06F30/398 ,  H01L27/02

    Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes receiving an integrated circuit layout, inserting, into the integrated circuit layout, a design containing a first set of Front-End Of Line (FEOL) shapes of an integrated circuit and a first set of Back-End Of Line (BEOL) shapes of the integrated circuit, inserting, into the integrated circuit layout, a set of cells containing a second set of FEOL shapes of the integrated circuit and a second set of BEOL shapes of the integrated circuit, removing a subset of the second set of BEOL shapes that conflict with the design, and providing the integrated circuit layout that includes the design and the set of cells for fabrication of the integrated circuit. The second set of FEOL shapes includes contact shapes that define contacts of the integrated circuit.

    Integrated circuit layouts with fill feature shapes
    8.
    发明授权
    Integrated circuit layouts with fill feature shapes 有权

    公开(公告)号：US11334703B2

    公开(公告)日：2022-05-17

    申请号：US15637484

    申请日：2017-06-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Cheng Yeh ,  Yen-Sen Wang ,  Ming-Yi Lin

    IPC: G06F30/392 ,  G06F30/398 ,  H01L27/02 ,  G06F30/394

    Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.

    Cell boundary layout
    9.
    发明授权
    Cell boundary layout 有权
    单元格边界布局

    公开(公告)号：US09405879B2

    公开(公告)日：2016-08-02

    申请号：US14231858

    申请日：2014-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Sen Wang ,  Ting Yu Chen ,  Ken-Hsien Hsieh ,  Ming-Yi Lin ,  Chen-Hung Lu

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5081 ,  G06F9/455 ,  G06F17/5068 ,  G06F17/5072

    Abstract: Some embodiments relate to a method of hierarchical layout design, comprising forming a layout of an integrated circuit (IC) according to a design rule that specifies a minimum design rule distance between a neighboring layout features within the IC. Forming the layout comprises forming first and second standard cells having first and second layout features, respectively, that about one-another so that a distance between the first and second layout features is less than the minimum design rule distance. The method further comprises configuring design rule checking (DRC) to ignore this fail. Instead, the layout is modified with an automated layout tool by merging the first and second layout features, or by removing a portion of the first or second layout feature to increase the distance between the first and second layout features to be greater than or equal to the minimum distance.

    Abstract translation: 一些实施例涉及分层布局设计的方法，包括根据规定IC内的相邻布局特征之间的最小设计规则距离的设计规则来形成集成电路（IC）的布局。 形成布局包括分别形成具有第一和第二布局特征的第一和第二标准单元，使得第一和第二布局特征之间的距离小于最小设计规则距离。 该方法还包括配置设计规则检查（DRC）以忽略该失败。 相反，通过合并第一和第二布局特征，或者通过移除第一或第二布局特征的一部分来增加第一和第二布局特征之间的距离来大于或等于 最小距离。

    CUT MASK DESIGN LAYERS TO PROVIDE COMPACT CELL HEIGHT
    10.
    发明申请
    CUT MASK DESIGN LAYERS TO PROVIDE COMPACT CELL HEIGHT 有权
    切割面板设计层提供紧凑的细胞高度

    公开(公告)号：US20150286765A1

    公开(公告)日：2015-10-08

    申请号：US14247409

    申请日：2014-04-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Sen Wang ,  Ming-Yi Lin ,  Chen-Hung Lu ,  Jyh-Kang Ting

    IPC: G06F17/50

    CPC classification number: G03F1/00 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874

    Abstract: Some embodiments relate to a method of designing an integrated circuit layout. In this method, a plurality of design shapes are provided on different design layers over an active area within a graphical representation of the layout. A connection extends perpendicularly between a first design shape formed on a first design layer and a second design shape formed on the first design layer. First and second cut mask shapes on first and second cut mask design layers, respectively, are generated. The first cut shape removes portions of the first design layer and the second cut shape removes portions of the second design layer.

    Abstract translation: 一些实施例涉及设计集成电路布局的方法。 在该方法中，在布局的图形表示内的有效区域上，在不同的设计层上提供多个设计形状。 连接在形成在第一设计层上的第一设计形状和形成在第一设计层上的第二设计形状之间垂直延伸。 产生分别在第一和第二切割掩模设计层上的第一和第二切割掩模形状。 第一切割形状去除第一设计层的部分，并且第二切割形状去除第二设计层的部分。

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