公开(公告)号：US12100751B2

公开(公告)日：2024-09-24

申请号：US18123596

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02274 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US11302582B2

公开(公告)日：2022-04-12

申请号：US16686388

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/51

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US20200091006A1

公开(公告)日：2020-03-19

申请号：US16686408

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L27/088

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US11610982B2

公开(公告)日：2023-03-21

申请号：US17140897

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US11532509B2

公开(公告)日：2022-12-20

申请号：US16884837

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20220367261A1

公开(公告)日：2022-11-17

申请号：US17813806

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing CO., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/423

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US20210134799A1

公开(公告)日：2021-05-06

申请号：US17120921

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L21/324 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/321 ,  H01L21/027

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US20240371981A1

公开(公告)日：2024-11-07

申请号：US18775706

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US20240363424A1

公开(公告)日：2024-10-31

申请号：US18769858

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsin-Han Tsai ,  Wei-Chin Lee ,  Chia-Ching Lee ,  Hung-Chin Chung ,  Cheng-Lung Hung ,  Da-Yuan Lee

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/42372

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US12087637B2

公开(公告)日：2024-09-10

申请号：US17120499

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsin-Han Tsai ,  Wei-Chin Lee ,  Chia-Ching Lee ,  Hung-Chin Chung ,  Cheng-Lung Hung ,  Da-Yuan Lee

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/42372

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.