公开(公告)号：US11239328B2

公开(公告)日：2022-02-01

申请号：US16926698

申请日：2020-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Sheng Chuang ,  You-Hua Chou ,  Ming-Chi Huang

IPC: H01L29/40 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/67 ,  H01L21/677 ,  H01L21/311 ,  H01L29/78 ,  H01L29/08

Abstract: A transistor includes a silicon germanium layer, a gate stack, and source and drain features. The silicon germanium layer has a channel region. The silicon germanium layer has a first silicon-to-germanium ratio. The gate stack is disposed over the channel region of the silicon germanium layer and includes a silicon germanium oxide layer over and in contact with the channel region of the silicon germanium layer, a high-κ dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-κ dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio.

公开(公告)号：US20210134799A1

公开(公告)日：2021-05-06

申请号：US17120921

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L21/324 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/321 ,  H01L21/027

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US12015077B2

公开(公告)日：2024-06-18

申请号：US17676335

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/82345 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/0276 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/6656 ,  H01L29/66636

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US11502080B2

公开(公告)日：2022-11-15

申请号：US17120921

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Cheng-Yen Tsai ,  Ming-Chi Huang ,  Zoe Chen ,  Wei-Chin Lee ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Weng Chang ,  Ching-Hwanq Su

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L21/324 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/321 ,  H01L21/027

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on an interface layer; forming a doping layer on the gate dielectric layer, the doping layer including a dipole-inducing element; annealing the doping layer to drive the dipole-inducing element through the gate dielectric layer to a first side of the gate dielectric layer adjacent the interface layer; removing the doping layer; forming a sacrificial layer on the gate dielectric layer, a material of the sacrificial layer reacting with residual dipole-inducing elements at a second side of the gate dielectric layer adjacent the sacrificial layer; removing the sacrificial layer; forming a capping layer on the gate dielectric layer; and forming a gate electrode layer on the capping layer.

公开(公告)号：US11887896B2

公开(公告)日：2024-01-30

申请号：US17838495

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Chi Huang ,  Ying-Liang Chuang

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/823821

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

公开(公告)号：US11682669B2

公开(公告)日：2023-06-20

申请号：US17446900

申请日：2021-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31111 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L21/823828

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US11362006B2

公开(公告)日：2022-06-14

申请号：US16889160

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Hsu ,  Ming-Chi Huang ,  Ying-Liang Chuang

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L21/28

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

公开(公告)号：US11257924B2

公开(公告)日：2022-02-22

申请号：US16746097

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US11189714B2

公开(公告)日：2021-11-30

申请号：US16928423

申请日：2020-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/49 ,  H01L29/08 ,  H01L29/165 ,  H01L29/51

Abstract: Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.

公开(公告)号：US10290716B2

公开(公告)日：2019-05-14

申请号：US15663791

申请日：2017-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Sheng Chuang ,  You-Hua Chou ,  Ming-Chi Huang

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/677 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8234

Abstract: A semiconductor device has a semiconductor substrate. A silicon germanium layer is disposed on the semiconductor substrate. The silicon germanium layer has a first silicon-to-germanium ratio. A first gate structure is disposed on the silicon germanium layer, and the first gate structure includes an interfacial layer on the silicon germanium layer. The interface layer has a second silicon-to-germanium ratio substantially the same as the first silicon-to-germanium ratio of the silicon germanium layer. The first gate structure also includes a high-dielectric layer on the interfacial layer and a first gate electrode on the high-κ dielectric layer.