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公开(公告)号：US10692817B2
公开(公告)日：2020-06-23
申请号：US16388635
申请日：2019-04-18
发明人： Shih-Ya Huang , Chung-Hao Tsai , Chuei-Tang Wang , Chen-Hua Yu , Chih-Yuan Chang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/552 , H01L23/528 , H01L23/00 , H01L23/522 , H01L23/538 , H01L23/50 , H01L21/683 , H01L21/56 , H01L23/31
摘要： A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
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公开(公告)号：US10269728B2
公开(公告)日：2019-04-23
申请号：US15950722
申请日：2018-04-11
发明人： Shih-Ya Huang , Chung-Hao Tsai , Chuei-Tang Wang , Chen-Hua Yu , Chih-Yuan Chang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/552 , H01L23/528 , H01L23/00 , H01L23/522 , H01L21/56
摘要： A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
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公开(公告)号：US20220320019A1
公开(公告)日：2022-10-06
申请号：US17218059
申请日：2021-03-30
发明人： Chih-Yuan Chang , Jiun-Yi Wu , Chien-Hsun Lee , Chung-Shi Liu , Chen-Hua Yu
摘要： A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.
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公开(公告)号：US10559517B2
公开(公告)日：2020-02-11
申请号：US16204953
申请日：2018-11-29
发明人： Ying-Chih Hsu , Alan Roth , Chuei-Tang Wang , Chih-Yuan Chang , Eric Soenen , Chih-Lin Chen
IPC分类号： H01L23/367 , H01L23/48 , H01L23/498 , H01L23/538 , H01L21/48
摘要： An integrated circuit (IC) package structure includes an electrical signal path, a low thermal resistance path and a substrate that includes a first device and a second device. The first device and the second device are part of an IC chip. The electrical signal path is from the first device to a top surface of the IC chip. The low thermal resistance path extends from the second device to the top surface of the IC chip. The low thermal resistance path is electrically isolated from the electrical signal path. The second device is thermally coupled to the first device by a low thermal resistance substrate path.
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公开(公告)号：US20190252326A1
公开(公告)日：2019-08-15
申请号：US16388635
申请日：2019-04-18
发明人： Shih-Ya Huang , Chung-Hao Tsai , Chuei-Tang Wang , Chen-Hua Yu , Chih-Yuan Chang
IPC分类号： H01L23/552 , H01L23/522 , H01L23/528 , H01L23/00 , H01L23/538
摘要： A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
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公开(公告)号：US20180082978A1
公开(公告)日：2018-03-22
申请号：US15822695
申请日：2017-11-27
CPC分类号： H01L24/98 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/5389 , H01L24/02 , H01L24/03 , H01L24/16 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/97 , H01L2924/1427
摘要： A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
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公开(公告)号：US09893042B2
公开(公告)日：2018-02-13
申请号：US15147617
申请日：2016-05-05
IPC分类号： H01L23/02 , H01L23/22 , H01L23/48 , H01L21/44 , H01L21/50 , H01L25/18 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/50 , H01L23/00 , H01L25/00
CPC分类号： H01L25/18 , H01L21/56 , H01L21/563 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L23/3675 , H01L23/481 , H01L23/50 , H01L24/02 , H01L24/19 , H01L24/20 , H01L24/89 , H01L25/50 , H01L2224/0231 , H01L2224/02372 , H01L2224/0239 , H01L2224/04105 , H01L2224/12105 , H01L2224/13025 , H01L2224/16227 , H01L2224/24137 , H01L2224/73204 , H01L2224/73259 , H01L2224/80894 , H01L2924/01013 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/06 , H01L2924/07025 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1427 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15321 , H01L2924/18162
摘要： A method and device are provided wherein a first semiconductor device and a via are encapsulated with an encapsulant. A redistribution layer connects the first semiconductor device to a second semiconductor device. In a particular embodiment the first semiconductor device is an integrated voltage regulator and the second semiconductor device is a logic device such as a central processing unit.
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公开(公告)号：US20170170155A1
公开(公告)日：2017-06-15
申请号：US15147617
申请日：2016-05-05
IPC分类号： H01L25/18 , H01L23/48 , H01L23/00 , H01L23/367 , H01L21/56 , H01L25/00 , H01L23/31 , H01L23/50
CPC分类号： H01L25/18 , H01L21/56 , H01L21/563 , H01L21/568 , H01L23/3128 , H01L23/3135 , H01L23/3142 , H01L23/3675 , H01L23/481 , H01L23/50 , H01L24/02 , H01L24/19 , H01L24/20 , H01L24/89 , H01L25/50 , H01L2224/0231 , H01L2224/02372 , H01L2224/0239 , H01L2224/04105 , H01L2224/12105 , H01L2224/13025 , H01L2224/16227 , H01L2224/24137 , H01L2224/73204 , H01L2224/73259 , H01L2224/80894 , H01L2924/01013 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/06 , H01L2924/07025 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1427 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15321 , H01L2924/18162
摘要： A method and device are provided wherein a first semiconductor device and a via are encapsulated with an encapsulant. A redistribution layer connects the first semiconductor device to a second semiconductor device. In a particular embodiment the first semiconductor device is an integrated voltage regulator and the second semiconductor device is a logic device such as a central processing unit.
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9.发明公开公开(公告)号：US20240321757A1
公开(公告)日：2024-09-26
申请号：US18733870
申请日：2024-06-05
发明人： Chuei-Tang Wang , Chen-Hua Yu , Chung-Shi Liu , Chih-Yuan Chang , Jiun-Yi Wu , Jeng-Shien Hsieh , Tin-Hao Kuo
IPC分类号： H01L23/538 , H01L21/48 , H01L21/683 , H01L23/00 , H01L23/31 , H01L25/065
CPC分类号： H01L23/5385 , H01L21/4853 , H01L21/6835 , H01L23/3128 , H01L23/5386 , H01L23/5387 , H01L24/20 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L2224/24226 , H01L2224/82005 , H01L2924/3511
摘要： A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.
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公开(公告)号：US11658134B2
公开(公告)日：2023-05-23
申请号：US17218059
申请日：2021-03-30
发明人： Chih-Yuan Chang , Jiun-Yi Wu , Chien-Hsun Lee , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/00 , H01L23/48 , H01L23/64 , H01L23/00 , H01L23/14 , H01L23/498 , H01L49/02 , H01L21/48 , H03H7/01
CPC分类号： H01L23/645 , H01L21/4857 , H01L23/145 , H01L23/49822 , H01L23/49838 , H01L24/16 , H01L28/10 , H01L28/40 , H03H7/0115 , H01L2224/16227 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103
摘要： A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.
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