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公开(公告)号：US20240332235A1
公开(公告)日：2024-10-03
申请号：US18741188
申请日：2024-06-12
发明人： Hui-Min HUANG , Ming-Da CHENG , Wei-Hung LIN , Chang-Jung HSUEH , Kai-Jun ZHAN , Yung-Sheng LIN
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/13006 , H01L2224/13009 , H01L2224/13018 , H01L2224/16227
摘要： A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.
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公开(公告)号：US20240266190A1
公开(公告)日：2024-08-08
申请号：US18642173
申请日：2024-04-22
发明人： Wen-Hsiung LU , Ming-Da CHENG , Su-Fei LIN , Hsu-Lun LIU , Chien-Pin CHAN , Yung-Sheng LIN
IPC分类号： H01L21/48 , C25D5/00 , H01L23/00 , H01L23/498 , H01L23/538
CPC分类号： H01L21/4853 , C25D5/60 , H01L21/486 , H01L23/49811 , H01L23/5384 , H01L24/14
摘要： In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
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公开(公告)号：US20240047403A1
公开(公告)日：2024-02-08
申请号：US18484609
申请日：2023-10-11
发明人： Neng-Chieh CHANG , Po-Hao TSAI , Ming-Da CHENG , Wen-Hsiung LU , Hsu-Lun LIU
CPC分类号： H01L24/20 , H01L24/19 , H01L24/24 , H01L24/82 , H01L21/561 , H01L25/105 , H01L24/96 , H01L2225/1058 , H01L2224/214 , H01L2224/215 , H01L2924/01029 , H01L2924/01013 , H01L24/13 , H01L2224/13024 , H01L24/04 , H01L24/05 , H01L2224/0401 , H01L2224/05569 , H01L2224/19 , H01L2224/24175 , H01L2224/821 , H01L2225/1035
摘要： A semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure further includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.
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公开(公告)号：US20240047397A1
公开(公告)日：2024-02-08
申请号：US18123794
申请日：2023-03-20
发明人： Bo-Yu CHIU , Pei-Wei LEE , Fu Wei LIU , Yun-Chung WU , Hao Chun YANG , Chin-Yu KU , Ming-Da CHENG , Ming-Ji LII
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/05 , H01L2224/02235 , H01L2224/10122 , H01L2224/0401 , H01L2224/05647 , H01L2224/05166 , H01L2224/05184 , H01L2224/05186 , H01L2224/05147 , H01L2224/05124 , H01L2224/05144 , H01L2224/11011
摘要： A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.
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公开(公告)号：US20200168583A1
公开(公告)日：2020-05-28
申请号：US16774983
申请日：2020-01-28
发明人： Yu-Feng CHEN , Chun-Hung LIN , Han-Ping PU , Ming-Da CHENG , Kai-Chiang WU
摘要： A semiconductor device includes a first semiconductor die package. The first semiconductor package includes a molding compound, and a conductive element in the molding compound, wherein a top surface of the conductive element is above or co-planar with a top-most surface of the molding compound. The semiconductor device further includes a second semiconductor die package The second semiconductor package includes a plurality of copper-containing contacts on a single metal pad, wherein each of the plurality of copper-containing contacts is bonded to the conductive element.
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公开(公告)号：US20240096787A1
公开(公告)日：2024-03-21
申请号：US18522622
申请日：2023-11-29
发明人： Ming-Da CHENG , Wei-Hung LIN , Hui-Min HUANG , Chang-Jung HSUEH , Po-Hao TSAI , Yung-Sheng LIN
IPC分类号： H01L23/522 , H01L21/48 , H01L23/00
CPC分类号： H01L23/5226 , H01L21/486 , H01L24/14
摘要： A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.
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公开(公告)号：US20230386964A1
公开(公告)日：2023-11-30
申请号：US17829243
申请日：2022-05-31
发明人： Chang-Jung HSUEH , Yen Wei CHANG , Cheng-Nan LIN , Wei-Hung LIN , Ming-Da CHENG
IPC分类号： H01L23/373 , H01L21/285 , H01L21/02
CPC分类号： H01L23/3736 , H01L21/2855 , H01L21/02052
摘要： In a method of forming a heat dissipating structure for a semiconductor chip, a soldering material is disposed on a top surface of the semiconductor chip. A first region of metal plating is formed on a surface of a lid. The first region has a first width and a first length. The first width is larger than a second width of the top surface of the semiconductor chip and the first length is larger than a second length of the top surface of the semiconductor chip. The lid is placed over the semiconductor chip so that the first region of metal plating of the lid is disposed over the soldering material to bond the lid to the semiconductor chip by a soldering material layer having an inverted trapezoidal shape between the lid and the top surface of the semiconductor chip.
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公开(公告)号：US20230098830A1
公开(公告)日：2023-03-30
申请号：US18077778
申请日：2022-12-08
发明人： Yi-Da TSAI , Cheng-Ping LIN , Wei-Hung LIN , Chih-Wei LIN , Ming-Da CHENG , Ching-Hua HSIEH , Chung-Shi LIU
IPC分类号： H01L23/538 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/29 , H01L23/31 , H01L21/683 , H01L25/00 , H01L25/065
摘要： Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.
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公开(公告)号：US20230067826A1
公开(公告)日：2023-03-02
申请号：US17460647
申请日：2021-08-30
发明人： Neng-Chieh CHANG , Po-Hao TSAI , Ming-Da CHENG , Wen-Hsiung LU , Hsu-Lun LIU
摘要： A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.
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公开(公告)号：US20220278071A1
公开(公告)日：2022-09-01
申请号：US17370249
申请日：2021-07-08
发明人： Kai Jun ZHAN , Chang-Jung HSUEH , Hui-Min HUANG , Wei-Hung LIN , Ming-Da CHENG
IPC分类号： H01L23/00
摘要： An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.
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