公开(公告)号：US11355399B2

公开(公告)日：2022-06-07

申请号：US16878005

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yu-Lien Huang ,  Ching-Feng Fu ,  Huan-Just Lin ,  Fu-Sheng Li ,  Tsai-Jung Ho ,  Bor Chiuan Hsieh ,  Guan-Xuan Chen ,  Guan-Ren Wang

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

公开(公告)号：US20210335673A1

公开(公告)日：2021-10-28

申请号：US17166548

申请日：2021-02-03

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yu-Lien Huang ,  Ching-Feng Fu ,  Huan-Just Lin ,  Che-Ming Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

公开(公告)号：US09577093B2

公开(公告)日：2017-02-21

申请号：US14876855

申请日：2015-10-07

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Cheng-Tung Lin ,  Teng-Chun Tsai ,  Li-Ting Wang ,  De-Fang Chen ,  Bing-Hung Chen ,  Huang-Yi Huang ,  Hui-Cheng Chang ,  Huan-Just Lin ,  Ming-Hsing Tsai

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/76237 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/26566 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

Abstract translation: 根据示例性实施例，提供了形成半导体器件的方法。 该方法包括：在衬底上提供垂直结构; 在垂直结构上形成蚀刻停止层; 在所述蚀刻停止层上形成氧化物层; 在氧化物层上进行化学机械抛光并停止在蚀刻停止层上; 蚀刻氧化物层和蚀刻停止层以暴露垂直结构的侧壁并形成隔离层; 氧化垂直结构的侧壁并通过使用聚簇氧掺杂处理将氧掺杂到隔离层中。

公开(公告)号：US12219882B2

公开(公告)日：2025-02-04

申请号：US17230640

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Hsing-Hsiang Wang ,  Yu-Feng Yin ,  Jiann-Horng Lin ,  Huan-Just Lin

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.

公开(公告)号：US11127837B2

公开(公告)日：2021-09-21

申请号：US16665011

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Ching-Feng Fu ,  Yu-Chan Yen ,  Chih-Hsin Ko ,  Chun-Hung Lee ,  Huan-Just Lin ,  Hui-Cheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/00 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L21/311

Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.

公开(公告)号：US20200058765A1

公开(公告)日：2020-02-20

申请号：US16665011

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Ching-Feng Fu ,  Yu-Chan Yen ,  Chih-Hsin Ko ,  Chun-Hung Lee ,  Huan-Just Lin ,  Hui-Cheng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L23/00

Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.

公开(公告)号：US09805968B2

公开(公告)日：2017-10-31

申请号：US15430614

申请日：2017-02-13

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Cheng-Tung Lin ,  Teng-Chun Tsai ,  Li-Ting Wang ,  De-Fang Chen ,  Bing-Hung Chen ,  Huang-Yi Huang ,  Hui-Cheng Chang ,  Huan-Just Lin ,  Ming-Hsing Tsai

IPC: H01L27/092 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L21/76237 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/26566 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827

Abstract: According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.

公开(公告)号：US09614054B2

公开(公告)日：2017-04-04

申请号：US14979831

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： De-Fang Chen ,  Teng-Chun Tsai ,  Cheng-Tung Lin ,  Li-Ting Wang ,  Chun-Hung Lee ,  Ming-Ching Chang ,  Huan-Just Lin

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L29/6653 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

公开(公告)号：US09343412B2

公开(公告)日：2016-05-17

申请号：US14178399

申请日：2014-02-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Ching-Feng Fu ,  Yu-Chan Yen ,  Chih-Hsin Ko ,  Chun-Hung Lee ,  Huan-Just Lin ,  Hui-Cheng Chang

IPC: H01L21/306 ,  H01L27/12 ,  H01L23/00 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/31144 ,  H01L23/564 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a MOSFET structure is provided. In the method, an epitaxial layer is formed. A cap layer is formed above the epitaxial layer. A first trench is formed above the epitaxial layer. A protection layer is deposited within the first trench. The protection layer is a material selected from the group consisting of germanium and silicon-germanium.

Abstract translation: 提供一种形成MOSFET结构的方法。 在该方法中，形成外延层。 在外延层上形成覆盖层。 在外延层上形成第一沟槽。 保护层沉积在第一沟槽内。 保护层是选自锗和硅 - 锗的材料。

公开(公告)号：US12142532B2

公开(公告)日：2024-11-12

申请号：US18188710

申请日：2023-03-23

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yu-Lien Huang ,  Ching-Feng Fu ,  Huan-Just Lin ,  Che-Ming Hsu

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/94

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.