公开(公告)号：US12218214B2

公开(公告)日：2025-02-04

申请号：US17231925

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

公开(公告)号：US12190931B2

公开(公告)日：2025-01-07

申请号：US18336386

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Peng-Chun Liou ,  Zhiqiang Wu ,  Chung-Wei Wu ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C11/22 ,  H10B51/20

Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

公开(公告)号：US12166089B2

公开(公告)日：2024-12-10

申请号：US18352289

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Nuo Xu ,  Zhiqiang Wu

IPC: G11C11/00 ,  G11C11/22 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

Abstract: A method includes: providing a substrate including a planar portion and a mesa portion over the planar portion; depositing an oxide layer over the mesa portion; depositing a ferroelectric material strip over the oxide layer and aligned with the mesa portion; and depositing a gate strip crossing the ferroelectric material strip and over the oxide layer.

公开(公告)号：US20240387736A1

公开(公告)日：2024-11-21

申请号：US18785076

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Chiang ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

公开(公告)号：US20240381783A1

公开(公告)日：2024-11-14

申请号：US18778989

申请日：2024-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Nuo Xu ,  Yuan Hao Chang ,  Po-Sheng Lu ,  Zhiqiang Wu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: An MRAM cell block and a magnetic shielding structure for the MRAM cell block are incorporated into a metal interconnect of an integrated circuit (IC) device. The magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. The magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. The wires and vias may also include a metal that is more conductive than the magnetic shielding material. The metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. The MRAM cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-D IC device that includes a second substrate having a conventional metal interconnect.

公开(公告)号：US12107054B2

公开(公告)日：2024-10-01

申请号：US18173080

申请日：2023-02-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Nuo Xu ,  Yuan-Hao Chang ,  Po-Sheng Lu ,  Zhiqiang Wu

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/13005 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1435

Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.

公开(公告)号：US20240313067A1

公开(公告)日：2024-09-19

申请号：US18669199

申请日：2024-05-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Tien Tung ,  Szu-Wei Huang ,  Zhi-Ren Xiao ,  Yin-Chuan Chuang ,  Yung-Chien Huang ,  Kuan-Ting Liu ,  Tzer-Min Shen ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/40 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L29/401 ,  H01L21/32053 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

公开(公告)号：US11929409B2

公开(公告)日：2024-03-12

申请号：US17966086

申请日：2022-10-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/45

Abstract: Semiconductor device includes a substrate having multiple fins formed from a substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin, a second epitaxial layer formed on the first epitaxial layer, and a third epitaxial layer formed on the second epitaxial layer, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion; a fourth epitaxial layer formed on the third epitaxial layer, a second source/drain feature adjacent the first source/drain feature, comprising a first epitaxial layer in contact with a second fin, a second epitaxial layer formed on the first epitaxial layer of the second source/drain feature, a third epitaxial layer formed on the second epitaxial layer of the second source/drain feature, the third epitaxial layer comprising a center portion and an edge portion that is at a different height than the center portion of the third epitaxial layer of the second source/drain feature; and a fourth epitaxial layer formed on the third epitaxial layer of the second source/drain feature.

公开(公告)号：US11849589B2

公开(公告)日：2023-12-19

申请号：US17808635

申请日：2022-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Han-Jong Chia ,  Yu-Ming Lin ,  Zhiqiang Wu ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H10B51/30 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H01L49/02 ,  H10B53/30

CPC classification number: H10B51/30 ,  H01L28/90 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/6684 ,  H01L29/78391 ,  H10B53/30

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a first conductive region and a second conductive region at the first surface, wherein the first conductive region is apart from the second conductive region, a gate feature, wherein a top surface of the gate feature is above the first conductive region, a stack unit coupled to the first conductive region, wherein the stack unit includes a plurality of ferroelectric layers stacking with a plurality of metal layers, wherein each of the plurality of ferroelectric layers separates adjacent two metal layers.

公开(公告)号：US11716857B2

公开(公告)日：2023-08-01

申请号：US17351121

申请日：2021-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Chien Chiu ,  Meng-Han Lin ,  Chun-Fu Cheng ,  Han-Jong Chia ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H10B51/10 ,  H10B51/30

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.