公开(公告)号：US5705429A

公开(公告)日：1998-01-06

申请号：US467846

申请日：1995-06-06

申请人： Takahisa Yamaha ,  Satoshi Hibino ,  Masaru Naito

发明人： Takahisa Yamaha ,  Satoshi Hibino ,  Masaru Naito

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76877 ,  H01L21/2855

摘要： After forming a contact hole in an insulator layer, which is formed on a substrate covering an impurity doped region, a Ti film, a TiN film (or TiON film), and an Al alloy (for example, an alloy of Al--Si--Cu) layer are sputtered (consecutively from the bottom level) for forming a wiring material layer. A wiring layer is formed by patterning the wiring material layer in accordance with a wiring pattern. Portions with a 0% coverage of the Al alloy layer are eliminated by sputtering the Al alloy layer with a substrate temperature in a range between 100.degree.and 150.degree. C.

摘要翻译： 在形成在覆盖杂质掺杂区域的基板上的绝缘体层中形成接触孔，Ti膜，TiN膜（或TiON膜）和Al合金（例如，Al-Si- Cu）层（从底层连续地）溅射以形成布线材料层。 通过根据布线图案图案化布线材料层而形成布线层。 Al合金层的覆盖率为0％的部分通过溅射Al合金层，基板温度在100〜150℃的范围内。

公开(公告)号：US5716869A

公开(公告)日：1998-02-10

申请号：US711986

申请日：1996-09-10

申请人： Satoshi Hibino ,  Takahisa Yamaha

发明人： Satoshi Hibino ,  Takahisa Yamaha

IPC分类号： H01L21/28 ,  H01L21/203 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/283

CPC分类号： H01L21/76804 ,  H01L21/76843 ,  H01L21/76882 ,  H01L2924/0002 ,  Y10S438/908 ,  Y10S438/913

摘要： A method of manufacturing a semiconductor device having the steps of: forming an insulating layer on a substrate having a semiconductor surface; forming a contact hole in and through the insulating layer; forming a conductive film on the inner surface of the contact hole and on the surface of the insulating film; forming a vapor deposited titanium film on the inner wall of a vacuum chamber; placing the substrate formed with the conductive film in the vacuum chamber; and heating the substrate and reflowing the conductive film. A good wiring layer can be formed by suppressing generation of a void during a reflow process.

摘要翻译： 一种制造半导体器件的方法，具有以下步骤：在具有半导体表面的衬底上形成绝缘层; 在绝缘层中形成接触孔; 在接触孔的内表面和绝缘膜的表面上形成导电膜; 在真空室的内壁上形成蒸镀钛膜; 将形成有导电膜的基板放置在真空室中; 并加热衬底并回流导电膜。 可以通过在回流工艺期间抑制空隙的产生来形成良好的布线层。

公开(公告)号：US05997754A

公开(公告)日：1999-12-07

申请号：US994884

申请日：1997-12-19

申请人： Takahisa Yamaha ,  Masaru Naito

发明人： Takahisa Yamaha ,  Masaru Naito

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01B13/00

CPC分类号： H01L21/76882 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76828

摘要： A wiring layer 36A is formed by sputtering, reflowing and patterning of an Al alloy layer on insulating layers 32 and 34 covering the surface of a semiconductor substrate 30. A silicon oxide layer 38 is formed by coating a hydrogen silsesquioxane resin film flatly over the layer 36A and by successive heat treatment. Then a silicon oxide layer 40 is formed on the layer 38 by plasma-enhanced chemical vapor deposition. After formation of the desired connecting hole in an interlayer insulating layer made of a lamination of the layers 38 and 40, a wiring layer 46 connected with the layer 36A via the connecting hole is formed by sputtering, reflowing and patterning of an Al alloy layer. Results of the measurements of the resistance of the via chains having 20000 vias indicated that resistace rise has not been observed. A multi-layered wiring which is highly resistant to stress migration is provided.

摘要翻译： 通过在覆盖半导体基板30的表面的绝缘层32和34上溅射，回流和Al合金层的图案化形成布线层36A。通过在该层上平坦地涂覆氢倍半硅氧烷树脂膜来形成氧化硅层38 并通过连续热处理。 然后通过等离子体增强化学气相沉积在层38上形成氧化硅层40。 在由层38和40的叠层形成的层间绝缘层中形成所需的连接孔之后，通过溅射，回流和Al合金层的图案化形成经由连接孔与层36A连接的布线层46。 具有20000个通孔的通孔链的电阻测量结果表明，没有观察到电阻上升。 提供了高度耐应力迁移的多层布线。

公开(公告)号：US5641993A

公开(公告)日：1997-06-24

申请号：US375125

申请日：1995-01-17

申请人： Takahisa Yamaha ,  Masaru Naito

发明人： Takahisa Yamaha ,  Masaru Naito

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/53214 ,  H01L2924/0002

摘要： On an insulating film covering the surface of a semiconductor substrate, a lower wiring layer made of Al or Al alloy is formed. An insulating film having a contact hole is formed on the lower wiring layer and the substrate. An upper wiring layer made of Al or Al alloy is formed on the insulating film and connected to the lower wiring layer via the contact hole. In such a multilayered wiring structure, the size of Al grain of the lower wiring layer, at least at the surface just under the contact hole, is made smaller than the bottom size of the contact hole. With this setting, Al atoms are supplied sufficiently from the lower wiring layer to the interface between the lower and upper wiring layers, preventing wiring disconnection caused by the peeling off of the interface.

摘要翻译： 在覆盖半导体基板的表面的绝缘膜上形成由Al或Al合金制成的下布线层。 在下布线层和基板上形成具有接触孔的绝缘膜。 在绝缘膜上形成由Al或Al合金制成的上部布线层，并通过接触孔与下部布线层连接。 在这种多层布线结构中，至少在接触孔下面的下表面层的Al颗粒的尺寸小于接触孔的底部尺寸。 通过这种设置，从下布线层到下布线层和上布线层之间的界面充分地供给Al原子，防止由界面剥离引起的布线断线。

公开(公告)号：US5885857A

公开(公告)日：1999-03-23

申请号：US7619

申请日：1998-01-15

申请人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

发明人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

IPC分类号： H01L23/52 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L21/283 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L23/3171 ,  H01L2924/0002

摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

摘要翻译： 一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。 在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。 作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。 也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

公开(公告)号：US5428251A

公开(公告)日：1995-06-27

申请号：US227685

申请日：1994-04-14

申请人： Masaru Naito ,  Takahisa Yamaha

发明人： Masaru Naito ,  Takahisa Yamaha

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/417

CPC分类号： H01L23/53214 ,  H01L2924/0002

摘要： In a multi-layer wiring structure of an integrated circuit device, occurrence of voids due to electromigration in the vicinity of an interface between upper and lower wiring layers is suppressed. The interface is cleaned in vacuum and grain size of the wiring layers is controlled. After an interlayer insulating film (16) having a connection hole (16A) is formed to cover a first wiring layer (14) of Al or an Al alloy, a second wiring layer (18) of Al or an Al alloy is formed and connected to the first wiring layer through the connection hole. When the second wiring layer is formed, grains (G.sub.2) of the second wiring layer are formed so as to be :respectively continuously adjacent to and substantially equal in size to grains (G.sub.1) of the first wiring layer which appear at the interface. This control may be done by suitably controlling the condition of sputter-etching the surface of the first wiring layer through the connection hole and the condition of sputtering the Al or Al alloy of tile second wiring layer.

摘要翻译： 在集成电路器件的多层布线结构中，抑制了由于上下布线层之间的界面附近的电迁移引起的空隙的发生。 界面在真空中清洁，并且控制布线层的晶粒尺寸。 在形成具有连接孔（16A）的层间绝缘膜（16）以覆盖Al或Al合金的第一布线层（14）之后，形成并连接Al或Al合金的第二布线层（18） 通过连接孔到第一布线层。 当第二布线层形成时，第二布线层的晶粒（G2）形成为分别连续地邻近于并且基本上等于出现在界面处的第一布线层的晶粒（G1）。 该控制可以通过适当地控制通过连接孔溅射蚀刻第一布线层的表面的条件和溅射第二布线层的Al或Al合金的条件来进行。

公开(公告)号：US6060390A

公开(公告)日：2000-05-09

申请号：US852097

申请日：1997-05-06

申请人： Masaru Naito ,  Takahisa Yamaha

发明人： Masaru Naito ,  Takahisa Yamaha

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/32051 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877

摘要： An interlayer insulating film made of insulating material is deposited on a substrate having a conductive region at least partially on the surface area thereof. A connection hole is formed through the interlayer insulating film, to expose the conductive region. The connection hole is filled with a plug made of conductive material. An underlying layer made of Ti is deposited over the whole surface of the substrate including the surface of the plug. A wiring layer made of Al alloy is deposited on the underlying layer, without exposing the substrate to the external atmosphere after the deposition of the Ti layer. The wiring layer is reflowed by heating the substrate. A method is provided which is capable of connecting an upper wiring layer to a lower conductive region without lowering resistance to electromigration and lowering step coverage.

摘要翻译： 由绝缘材料制成的层间绝缘膜至少部分地在其表面积上沉积在具有导电区域的基板上。 通过层间绝缘膜形成连接孔，露出导电区域。 连接孔填充有由导电材料制成的插头。 由Ti构成的下层被沉积在包括插塞表面的基片的整个表面上。 由Al合金制成的布线层沉积在下层上，而在Ti层沉积之后不将基片暴露于外部大气。 通过加热衬底来回流布线层。 提供一种能够将上层布线层连接到下导电区域而不降低电迁移阻力和降低台阶覆盖率的方法。

公开(公告)号：US5763936A

公开(公告)日：1998-06-09

申请号：US637227

申请日：1996-04-24

申请人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

发明人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

IPC分类号： H01L23/52 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/58 ,  H01L23/48 ,  H01L23/544

CPC分类号： H01L23/3171 ,  H01L2924/0002

摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

摘要翻译： 一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。 在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。 作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。 也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

公开(公告)号：US20060138662A1

公开(公告)日：2006-06-29

申请号：US11354134

申请日：2006-02-15

申请人： Takahisa Yamaha

发明人： Takahisa Yamaha

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

摘要： A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island shape formed on the insulating film; first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over the insulating film; second-level to n-level conductive pad layers formed on the interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer was formed; a plurality of small diameter first through holes from the first-level to (n−1) level formed through the first-level to (n−1) level interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer; a plurality of first contact plugs filled in the small diameter first through holes from the first-level to (n−1)-level, the first contact plugs at each level being conductive and electrically connecting two conductive pad layers adjacent along a normal to a surface of the semiconductor substrate, among the first-level to n-level conductive pad layers disposed in and on the first-level to (n−1)-level interlayer insulating films; an n-level interlayer insulating film formed on the (n−1)-level interlayer insulating film and covering the n-level conductive pad; a large diameter through hole formed though the n-level interlayer insulating film in an area corresponding to an area where the n-level conductive pad was formed; the large diameter through hole having a size corresponding to the n-level conductive pad to expose a substantial upper surface of the n-level conductive pad; and a bonding pad formed on the n-level interlayer insulating film and n-level conductive pad via the large diameter through hole.

公开(公告)号：US20050146042A1

公开(公告)日：2005-07-07

申请号：US11073753

申请日：2005-03-08

申请人： Takahisa Yamaha

发明人： Takahisa Yamaha

IPC分类号： B05D5/12 ,  B32B3/10 ,  B32B7/02 ,  H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

摘要： A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island shape formed on the insulating film; first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over the insulating film; second-level to n-level conductive pad layers formed on the interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer was formed; a plurality of small diameter first through holes from the first-level to (n−1) level formed through the first-level to (n−1) level interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer; a plurality of first contact plugs filled in the small diameter first through holes from the first-level to (n−1)-level, the first contact plugs at each level being conductive and electrically connecting two conductive pad layers adjacent along a normal to a surface of the semiconductor substrate, among the first-level to n-level conductive pad layers disposed in and on the first-level to (n−1)-level interlayer insulating films; an n-level interlayer insulating film formed on the (n−1)-level interlayer insulating film and covering the n-level conductive pad; a large diameter through hole formed though the n-level interlayer insulating film in an area corresponding to an area where the n-level conductive pad was formed; the large diameter through hole having a size corresponding to the n-level conductive pad to expose a substantial upper surface of the n-level conductive pad; and a bonding pad formed on the n-level interlayer insulating film and n-level conductive pad via the large diameter through hole.

摘要翻译： 一种半导体器件，具有形成在半导体衬底上的半导体衬底和接合焊盘部分，所述接合焊盘部分具有形成在所述半导体衬底上的绝缘膜和形成在所述绝缘膜上的大岛形状的第一级导电焊盘层 ; 在绝缘膜上形成的第一级至（n-1）级（n为3以上的整数）层间绝缘膜; 在通常对应于形成有第一导电焊盘层的区域的区域中在层间绝缘膜上形成的二级至n级导电焊盘层; 在通常对应于第一导电焊盘层的区域的区域中，通过第一级到（n-1）级的层间绝缘膜形成从第一级到第（n-1级）的多个小直径的第一通孔; 多个第一接触塞，其填充在从第一级到第（n-1）级的小直径第一通孔中，每个级的第一接触塞是导电的并且电连接沿着法线相邻的两个导电垫层 设置在第一级至（n-1）级层间绝缘膜中的第一级至第n级导电焊盘层中的半导体衬底的表面; 形成在（n-1）层间绝缘膜上并覆盖n级导电焊盘的n级层间绝缘膜; 在与形成有n级导电垫的区域对应的区域中形成有通过n级层间绝缘膜形成的大直径通孔; 所述大直径通孔具有对应于所述n级导电焊盘的尺寸，以露出所述n级导电焊盘的实质上表面; 以及通过大直径通孔形成在n级层间绝缘膜和n级导电焊盘上的接合焊盘。