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    Method of manufacturing active matrix substrate
    3.
    发明授权
    Method of manufacturing active matrix substrate 失效
    有源矩阵基板的制造方法

    公开(公告)号：US5821133A

    公开(公告)日：1998-10-13

    申请号：US576036

    申请日：1995-12-21

    申请人： Katsuhiro Kawai ,  Mikio Katayama ,  Satoshi Yabuta ,  Masaru Kajitani

    发明人： Katsuhiro Kawai ,  Mikio Katayama ,  Satoshi Yabuta ,  Masaru Kajitani

    IPC分类号： G02F1/136 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L21/786

    CPC分类号： H01L29/66765 ,  G02F1/1368 ,  H01L27/1214 ,  H01L29/458

    摘要： A simplified method of manufacturing an active matrix substrate is disclosed. Gate wires, gate electrodes, gate insulating films, an etching stopper layer, semiconductor layers and contact layers are formed on an electrically insulating substrate. Pixel electrode material films, second electrical conductor films and second insulating films are formed successively on the substrate. The second insulating film and the second electrical conductor film are simultaneously patterned, so that source wires, source electrodes and drain electrodes are formed from the second electrical conductor film, and a protective film from the second insulating film. Then, the pixel electrode material film is patterned thereby to form pixel electrodes in a plurality of regions defined by the gate wires and the source wires.

    摘要翻译： 公开了制造有源矩阵衬底的简化方法。 在绝缘基板上形成栅极线，栅电极，栅极绝缘膜，蚀刻停止层，半导体层和接触层。 在基板上依次形成像素电极材料膜，第二导电膜和第二绝缘膜。 同时对第二绝缘膜和第二导电膜进行构图，从而从第二导电膜形成源极线，源电极和漏电极以及来自第二绝缘膜的保护膜。 然后，对像素电极材料膜进行图案化，从而在由栅极线和源极线限定的多个区域中形成像素电极。

    Thin film transistor including oxidized film by oxidation of the surface of a channel area semiconductor
    4.
    发明授权
    Thin film transistor including oxidized film by oxidation of the surface of a channel area semiconductor 失效
    薄膜晶体管包括通过沟道区域半导体的表面氧化的氧化膜

    公开(公告)号：US5962896A

    公开(公告)日：1999-10-05

    申请号：US570013

    申请日：1995-12-14

    申请人： Satoshi Yabuta ,  Katsuhiro Kawai ,  Masaru Kajitani

    发明人： Satoshi Yabuta ,  Katsuhiro Kawai ,  Masaru Kajitani

    IPC分类号： G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01

    CPC分类号： H01L29/66765 ,  H01L29/78669

    摘要： A thin film transistor (TFT) has a substrate. There is provided on the substrate a gate electrode, a gate insulating layer, a semiconductor layer, ohmic contact layers, electrodes (i.e., a source electrode and a drain electrode), and a protective layer in this order. An oxidized film is provided on a channel area of the semiconductor layer. With the arrangement, it is possible, without providing a channel protective layer, to prevent undesirable etching to the channel area, thereby greatly reducing the number of defective products. Since it is not necessary to make the semiconductor layer thicker than is required, it is possible to minimize the occurrence that the TFT characteristic is affected by the projected light. In addition, it is possible to realize miniaturization and to get a great aperture ratio when used as a switching element in a liquid crystal display (LCD) device.

    摘要翻译： 薄膜晶体管（TFT）具有基板。 在基板上设置有栅电极，栅极绝缘层，半导体层，欧姆接触层，电极（即源电极和漏电极）以及保护层。 氧化膜设置在半导体层的沟道区上。 通过该布置，可以在不设置沟道保护层的情况下防止对沟道区域的不期望的蚀刻，从而大大减少缺陷产物的数量。 由于不需要使半导体层比所需的厚度更厚，所以可以最小化TFT特性受投影光的影响的发生。 此外，在液晶显示（LCD）装置中用作开关元件时，可以实现小型化并获得大的开口率。

    Matrix type display device
    5.
    发明授权
    Matrix type display device 失效
    矩阵式显示装置

    公开(公告)号：US5745201A

    公开(公告)日：1998-04-28

    申请号：US725261

    申请日：1996-10-02

    申请人： Katsuhiro Kawai ,  Satoshi Yabuta ,  Masaya Okamoto ,  Masaru Kajitani

    发明人： Katsuhiro Kawai ,  Satoshi Yabuta ,  Masaya Okamoto ,  Masaru Kajitani

    IPC分类号： G02F1/1343 ,  G02F1/13 ,  G02F1/1335 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  H01L21/336 ,  H01L29/786 ,  G02F1/1333

    CPC分类号： G02F1/1309 ,  G02F1/133512 ,  G02F2001/136268

    摘要： An object of the invention is to facilitate identifying the display color of each pixel during a test process and to apply a correction to a defective switching device in accordance with a test criterion established for each display color. On one transparent substrate, there are formed gate wiring and source wirings intersecting at right angles to each other so that insulation therebetween is maintained, and a pixel electrode and a TFT device are formed for each pixel, thus constructing one substrate member. On another transparent substrate, there is formed a counter electrode facing the pixel electrodes, and identifying means for identifying the display color of each pixel is formed on the side opposite from the side where the counter electrode is formed, the identifying means then being covered with a light-blocking member, thus constructing the another substrate member. The light-blocking member contains openings formed therethrough in portions facing the pixel electrodes. Since the display color of each pixel can be identified using the identifying means, a defective switching device in a pixel can be corrected in accordance with a correction criterion established for each display color.

    摘要翻译： 本发明的目的是便于在测试过程期间识别每个像素的显示颜色，并根据为每个显示颜色建立的测试标准对缺陷开关设备应用校正。 在一个透明基板上形成栅极布线和源极布​​线，彼此成直角交叉，从而保持它们之间的绝缘，并且为每个像素形成像素电极和TFT器件，从而构成一个基板部件。 在另一透明基板上形成面对像素电极的对置电极，并且在与形成对置电极的一侧相反的一侧形成用于识别每个像素的显示颜色的识别装置，然后识别装置被覆盖 遮光构件，从而构成另一基板构件。 遮光构件包括在与像素电极相对的部分中形成的开口。 由于可以使用识别装置来识别每个像素的显示颜色，所以可以根据为每个显示颜色建立的校正标准来校正像素中的有缺陷的切换装置。

    Method of ashing resist and apparatus therefor
    7.
    发明授权
    Method of ashing resist and apparatus therefor 失效
    抗灰化方法及其设备

    公开(公告)号：US5688410A

    公开(公告)日：1997-11-18

    申请号：US581197

    申请日：1995-12-29

    申请人： Masaru Kajitani ,  Satoshi Yabuta ,  Katsuhiro Kawai ,  Masaya Okamoto

    发明人： Masaru Kajitani ,  Satoshi Yabuta ,  Katsuhiro Kawai ,  Masaya Okamoto

    IPC分类号： H01L21/302 ,  G03F7/42 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311 ,  C23F1/00 ,  H01L21/306

    CPC分类号： H01L21/31138 ,  G03F7/427

    摘要： An object of the invention is to enhance the ashing speed of resist. A parallel plate electrode type plasma etching device is used in a mixed gas atmosphere of SF.sub.6 gas and O.sub.2 gas with the concentration of SF.sub.6 gas defined within 5 vol. % to 15 vol. %. A substrate to be treated, coated with a resist of hydrocarbon polymer is placed on a lower electrode. A high frequency electric power is applied to an upper electrode and lower electrode placed parallel to each other, and a plasma of mixed gas is generated in the reactor. A chemical reaction is induced in the resist and active ions of the plasma to vaporize and remove the resist.

    摘要翻译： 本发明的目的是提高抗蚀剂的灰化速度。 在SF6气体和O 2气体的混合气体气氛中使用平行平板电极型等离子体蚀刻装置，其中SF 6气体的浓度定义在5体积内。 ％至15体积 ％。 将待处理的基材，涂覆有碳氢聚合物的抗蚀剂放置在下电极上。 将高频电力施加到彼此平行放置的上电极和下电极，并且在反应器中产生混合气体的等离子体。 在等离子体的抗蚀剂和活性离子中引起化学反应以蒸发并除去抗蚀剂。

    Active matrix substrate and producing method of the same
    8.
    发明授权
    Active matrix substrate and producing method of the same 失效

    公开(公告)号：US06411348B1

    公开(公告)日：2002-06-25

    申请号：US08883593

    申请日：1997-06-26

    申请人： Katsuhiro Kawai ,  Shinya Yamakawa ,  Masaya Okamoto ,  Takayuki Shimada ,  Mikio Katayama

    发明人： Katsuhiro Kawai ,  Shinya Yamakawa ,  Masaya Okamoto ,  Takayuki Shimada ,  Mikio Katayama

    IPC分类号： G02F1136

    摘要： An active matrix is furnished with an insulating substrate; a plurality of scanning lines and signal lines provided on the insulating substrate in a matrix pattern; pixel electrodes provided in areas enclosed by the scanning lines and signal lines, respectively; switching elements electrically connected to the scanning lines, signal lines, and pixel electrodes, respectively; a resistance control element for electrically connecting two lines selected arbitrary from the scanning lines and signal lines while controlling its own resistance value in response to a voltage applied thereto. According to the above arrangement, it has become possible to increase a margin of the active matrix substrate for the static electricity and improve the production yield without increasing the number of the producing steps.

    Actived matrix substrate having a transistor with multi-layered ohmic contact
    10.
    发明授权
    Actived matrix substrate having a transistor with multi-layered ohmic contact 失效
    具有具有多层欧姆接触的晶体管的活性矩阵基板

    公开(公告)号：US5981972A

    公开(公告)日：1999-11-09

    申请号：US79149

    申请日：1998-05-15

    申请人： Katsuhiro Kawai ,  Shinya Yamakawa ,  Satoshi Yabuta ,  Atsushi Ban

    发明人： Katsuhiro Kawai ,  Shinya Yamakawa ,  Satoshi Yabuta ,  Atsushi Ban

    IPC分类号： G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/04

    CPC分类号： H01L29/66765 ,  G02F1/136227 ,  H01L29/4908 ,  H01L29/78669

    摘要： An active matrix substrate of a Pixel on Passivation structure includes TFTs and pixel electrodes on an interlayer insulating film over bus lines. The interlayer insulating film is formed of an organic insulating film, and the contact layer of the TFT has a double layer structure of a fine crystal silicon (n.sup.+) layer and an amorphous silicon (n.sup.+) layer the crystal silicon (n.sup.+) layer being placed on the side closer to the source electrode and the drain electrode, and the amorphous silicon (n.sup.+) layer being placed on the opposite side. This improves both the ON characteristics and the OFF characteristics of the TFT are improved, and the stable operative region of the active matrix substrate and the margin to accommodate to variations in threshold value due to aging are expanded, without substantial additional production costs and a decrease in productivity.

    摘要翻译： 钝化结构像素的有源矩阵基板在总线上的层间绝缘膜上包括TFT和像素电极。 层间绝缘膜由有机绝缘膜形成，TFT的接触层具有晶体硅（n +）层和非晶硅（n +）层的双层结构，晶体硅（n +）层被放置 在更靠近源电极和漏电极的一侧，并且非晶硅（n +）层位于相对侧。 这改善了TFT的ON特性和OFF特性，并且有效矩阵基板的稳定操作区域和裕度适应由于老化引起的阈值变化，而没有大量额外的生产成本和减少 在生产力。