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1.发明授权公开(公告)号：US06937088B2
公开(公告)日：2005-08-30
申请号：US10909419
申请日：2004-08-03
IPC分类号： G05F3/26 , G05F1/46 , G11C11/407 , H02M3/155 , H03F3/45 , H03K17/687 , H03K19/00 , G05F1/10
CPC分类号： G05F1/465
摘要： An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential ½ times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.
摘要翻译： 内部电源电位产生电路包括：控制电位发生电路，其具有串联连接在节点和接地电位线之间的四个MOS晶体管，以及控制上拉晶体管和下拉晶体管，以便在 输出节点与控制电位一致; 具有串联连接在规定节点和地电位线之间的四个MOS晶体管，并产生监视电位的监视电位发生电路; 产生电位为参考电位的1/2倍的电势分压电路; 以及VCC1发生电路，其控制规定电位的电位，以使监视电位成为基准电位。 因此，可以正确地控制输出电位。
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2.发明授权公开(公告)号：US06781443B2
公开(公告)日：2004-08-24
申请号：US10274890
申请日：2002-10-22
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.
摘要翻译： 内部电源电位产生电路包括：控制电位发生电路，其具有串联连接在节点和接地电位线之间的四个MOS晶体管，以及控制上拉晶体管和下拉晶体管，以便在 输出节点与控制电位一致; 具有串联连接在规定节点和地电位线之间的四个MOS晶体管，并产生监视电位的监视电位发生电路; 产生电位为参考电位1/2倍的电位分压电路; 以及VCC1发生电路，其控制规定电位的电位，以使监视电位成为基准电位。 因此，可以正确地控制输出电位。
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3.发明授权Semiconductor memory device having voltage down convertor reducing current consumption 有权具有降压转换器的半导体存储器件减少电流消耗公开(公告)号：US06262931B1
公开(公告)日：2001-07-17
申请号：US09539893
申请日：2000-03-31
IPC分类号： G11C800
摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.
摘要翻译： 控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。 因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。
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4.发明申请公开(公告)号：US20050007190A1
公开(公告)日：2005-01-13
申请号：US10909419
申请日：2004-08-03
IPC分类号： G05F3/26 , G05F1/46 , G11C11/407 , H02M3/155 , H03F3/45 , H03K17/687 , H03K19/00 , G05F1/10
CPC分类号： G05F1/465
摘要： An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.
摘要翻译： 内部电源电位产生电路包括：控制电位发生电路，其具有串联连接在节点和接地电位线之间的四个MOS晶体管，以及控制上拉晶体管和下拉晶体管，以便在 输出节点与控制电位一致; 具有串联连接在规定节点和地电位线之间的四个MOS晶体管，并产生监视电位的监视电位发生电路; 产生电位为参考电位1/2倍的电位分压电路; 以及VCC1发生电路，其控制规定电位的电位，以使监视电位成为基准电位。 因此，可以正确地控制输出电位。
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公开(公告)号：US20110193640A1
公开(公告)日：2011-08-11
申请号：US13021047
申请日：2011-02-04
申请人： Tsukasa OISHI , Katsuyoshi Mitsui , Naoki Otani
发明人： Tsukasa OISHI , Katsuyoshi Mitsui , Naoki Otani
IPC分类号： H03L7/099
摘要： This invention provides a semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A temperature sensor detects the ambient temperature of the high speed OCO and a voltage sensor detects the operating voltage of the high speed OCO. The power supply module includes a BGR and generates the reference voltage, reference current, and operating voltage of the high speed OCO, based on a primary reference voltage which is output by the BGR. A flash memory stores a table specifying trimming codes for the reference voltage and reference current, related to an ambient temperature and an operating voltage of the high speed OCO. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to the detected ambient temperature and operating voltage.
摘要翻译： 本发明提供了一种半导体器件，其被设计为防止提供给高速OCO的参考电压和参考电流随着环境温度的变化和/或外部电源电压的变化而变化，并且减小电路面积 电源模块。 高速OCO输出高速时钟，其大小由参考电流和参考电压决定。 温度传感器检测高速OCO的环境温度，电压传感器检测高速OCO的工作电压。 电源模块包括BGR，并基于由BGR输出的主参考电压产生高速OCO的参考电压，参考电流和工作电压。 闪速存储器存储一个表格，该表格指定与环境温度和高速OCO的工作电压相关的参考电压和参考电流的修整代码。 逻辑单元根据与检测到的环境温度和工作电压相关的参考电压和参考电流调整代码调整参考电流和参考电压的值。
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公开(公告)号：US07728678B2
公开(公告)日：2010-06-01
申请号：US12253636
申请日：2008-10-17
申请人： Katsuyoshi Mitsui
发明人： Katsuyoshi Mitsui
摘要： A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.
摘要翻译： 一种半导体器件包括：电压控制和振荡电路，其以根据第一控制电压的频率振荡以输出振荡信号;频率/电压转换电路，从所述电压控制和振荡电路接收所述振荡信号，并转换所述振荡频率 信号转换为电压，产生具有在由频率/电压转换电路转换的电压与先前产生的第二控制电压的电压之间的电平的新的第二控制电压的控制电压产生电路以及将第二 控制电压产生第一控制电压并将第一控制电压输出到电压控制和振荡电路。
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公开(公告)号：US5407867A
公开(公告)日：1995-04-18
申请号：US948528
申请日：1992-09-22
IPC分类号： C23C14/02 , C23C14/56 , C23C16/02 , C23C16/54 , H01L21/465
CPC分类号： C23C14/568 , C23C14/022 , C23C16/0236 , C23C16/54 , Y10S438/913
摘要： A method of and an apparatus for removing a naturally grown oxide film and contaminants on the surface of a semiconductor substrate and then forming a thin film on the cleaned surface. The semiconductor substrate is placed in a pretreatment chamber and then hydrogen chloride gas is introduced into the chamber. Then, the semiconductor substrate is heated at a temperature between 200.degree..about.700.degree. C. and the surface of the semiconductor substrate is irradiated with ultraviolet rays, whereby the naturally grown oxide film and other contaminants on the semiconductor substrate can be removed. Then, a thin film is formed on the cleaned surface of the semiconductor substrate by a CVD method or a sputter method. According to this method, the naturally oxide film and other contaminants can be removed from the surface of the semiconductor substrate at a low temperature and the thin film can be formed on the cleaned surface. As a result, an interface structure between the semiconductor substrate and the thin film can be controlled to be in a preferable state.
摘要翻译： 一种用于去除半导体衬底表面上的天然生长的氧化物膜和污染物，然后在清洁表面上形成薄膜的方法和设备。 将半导体基板放置在预处理室中，然后将氯化氢气体引入室中。 然后，在200℃〜700℃的温度下加热半导体衬底，用紫外线照射半导体衬底的表面，由此可以除去半导体衬底上的天然生长的氧化膜和其它污染物。 然后，通过CVD法或溅射法在半导体衬底的清洁表面上形成薄膜。 根据该方法，可以在低温下从半导体基板的表面去除天然氧化膜和其它污染物，并且可以在清洁的表面上形成薄膜。 结果，可以将半导体衬底和薄膜之间的界面结构控制在优选的状态。
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公开(公告)号：US5378923A
公开(公告)日：1995-01-03
申请号：US909324
申请日：1992-07-06
IPC分类号： H01L27/12 , H01L21/338 , H01L29/778 , H01L29/78 , H01L29/786 , H01L29/812 , H01L29/06 , H01L29/784
CPC分类号： H01L29/78612
摘要： Holes generated by impact ionization in a SOI-MOS transistor is removed from the channel region to improve the breakdown voltage between the source and drain. A channel region of the SOI-MOS transistor is formed of a p type silicon layer. A drain region is formed of an n type silicon layer. A source region adjacent to the channel region includes an n type germanium layer. The forbidden energy band gap width of the germanium is smaller than that of the silicon. The n type germanium layer is formed in at least a portion of the source region. This layer is formed by ion-implanting germanium into a portion of the silicon layer, or removing a portion of the silicon layer, followed by growing a germanium layer in an epitaxial manner thereabove.
摘要翻译： 在SOI-MOS晶体管中通过冲击电离产生的孔从沟道区域去除以改善源极和漏极之间的击穿电压。 SOI-MOS晶体管的沟道区域由p型硅层形成。 漏区由n型硅层形成。 与沟道区相邻的源极区包括n型锗层。 锗的禁带宽度窄于硅。 n型锗层形成在源区的至少一部分中。 该层通过将锗离子注入到硅层的一部分中，或者去除硅层的一部分，然后以其外延方式生长锗层而形成。
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9.发明授权MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof 失效具有p沟道MOS器件的MIS器件和具有LDD结构的n沟道MOS器件及其制造方法
公开(公告)号：US5296401A
公开(公告)日：1994-03-22
申请号：US973250
申请日：1992-11-09
申请人： Katsuyoshi Mitsui , Shigeki Komori
发明人： Katsuyoshi Mitsui , Shigeki Komori
IPC分类号： H01L21/8238 , H01L29/423 , H01L29/78 , H01L21/70
CPC分类号： H01L29/42376 , H01L21/823864 , H01L29/78 , H01L29/7836
摘要： In a CMOS semiconductor device, a pMOS transistor and an nMOS transistor are formed on a single substrate. Each of the source/drain regions of the nMOS transistor and the pMOS transistor has LDD structure composed of a combination of a low concentration impurity region and a high concentration impurity region. The low concentration impurity region of the LDD structure of the pMOS transistor is formed in a self-align manner by ion implantation using a sidewall spacer with relatively thick film thickness. The low concentration impurity region of the LDD structure of the nMOS transistor is formed in a self-align manner by ion implantation using a relatively thin sidewall spacer as a mask. The sidewall spacer with thick film thickness of the pMOS transistor restrains that the channel between the source/drain regions is shortened due to thermal diffusion to cause punch through. As for the sidewall spacer of the nMOS transistor, its film thickness is selected to effectively restrain hot carrier effect in the vicinity of the drain and restrain degradation of current handling capability due to parasitic resistance to the minimum.
摘要翻译： 在CMOS半导体器件中，在单个衬底上形成pMOS晶体管和nMOS晶体管。 nMOS晶体管和pMOS晶体管的源极/漏极区域中的每一个具有由低浓度杂质区域和高浓度杂质区域的组合构成的LDD结构。 pMOS晶体管的LDD结构的低浓度杂质区域通过使用具有相对厚的膜厚度的侧壁间隔件的离子注入以自对准的方式形成。 nMOS晶体管的LDD结构的低浓度杂质区域通过使用相对较薄的侧壁间隔物作为掩模的离子注入以自对准的方式形成。 具有pMOS晶体管的厚膜厚度的侧壁隔离层限制了源极/漏极区域之间的沟道由于热扩散而被缩短以引起穿通。 对于nMOS晶体管的侧壁间隔物，其膜厚度被选择为有效地抑制在漏极附近的热载流子效应，并且抑制由寄生电阻降到最小的电流处理能力的劣化。
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公开(公告)号：US5183771A
公开(公告)日：1993-02-02
申请号：US732541
申请日：1991-07-19
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： In an MIS transistor of a type having LDD and salicide structures, the location of the boundary between the high and low impurity density source/drain regions and the positions of the salicide layers on the source/drain regions are independently controlled during fabrication using a double gate sidewall structure. An MIS transistor improved thereby has its boundary between the high and low impurity density source/drain regions at or displaced toward the control gate electrode with respect to the interface of the double gate sidewall structure.
摘要翻译： 在具有LDD和自对准硅化物结构的MIS晶体管中，高和低杂质浓度源极/漏极区域之间的边界位置和源极/漏极区域上的自对准硅化物层的位置在制造期间被独立地控制，使用双 门侧壁结构。 因此，改善的MIS晶体管相对于双栅极侧壁结构的界面在其与控制栅电极之间或之后的高杂质浓度源极/漏极区域之间具有边界。
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