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1.发明授权System using timing information contained in data read from reproduction unit controlled by first oscillator to vary frequency of independent system clock signal 失效系统使用包含在从由第一振荡器控制的再现单元读取的数据中的定时信息来改变独立系统时钟信号的频率
公开(公告)号：US5630112A
公开(公告)日：1997-05-13
申请号：US301266
申请日：1994-09-06
申请人： Takuji Yoshida , Takayuki Uchida
发明人： Takuji Yoshida , Takayuki Uchida
CPC分类号： G06F3/0601 , G06F1/08 , G06F13/385 , G06F2003/0692
摘要： The present invention relates to a digital data processing apparatus for transferring digital data which is output from a disc reproduction section (15.sub.1) to a buffer memory (18)-equipped host processing section (13) and for making processing. By detecting a shift in frequency of an operation clock on the basis of an output of the disc reproduction section (15.sub.1) and varying the frequency of the operation clock of the host processing section (13) in accordance with a result of that detection, it is possible to prevent the memory (18) from being placed in an over- or an underflowed state and to perform a normal data reproduction.
摘要翻译： 本发明涉及一种数字数据处理装置，用于将从盘再现部分（151）输出的数字数据传送到缓冲存储器（18）的主机处理部分（13）并用于进行处理。 通过根据盘再现部（151）的输出检测操作时钟的频率偏移，并根据该检测结果改变主机处理部（13）的工作时钟的频率， 可以防止存储器（18）被置于上溢或下溢状态并执行正常的数据再现。
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公开(公告)号：US20110102242A1
公开(公告)日：2011-05-05
申请号：US12997814
申请日：2010-03-19
申请人： Shinichi Takeya , Kazuaki Kawabata , Kazuki Oosuga , Takuji Yoshida , Tomohiro Yoshida , Masato Niwa , Hideto Goto
发明人： Shinichi Takeya , Kazuaki Kawabata , Kazuki Oosuga , Takuji Yoshida , Tomohiro Yoshida , Masato Niwa , Hideto Goto
IPC分类号： G01S13/58
CPC分类号： G01S13/42 , G01S7/02 , G01S7/35 , G01S7/415 , G01S13/345 , G01S13/44 , G01S13/584 , G01S13/66
摘要： The present invention includes a transmitter/receiver 20 that transmits/receives an FMCW based sweep signal, a velocity grouping unit 36 that performs grouping of a target for each velocity range by a velocity of the target calculated based on the sweep signal from the transmitter/receiver, and a correlation tracking unit 37 that performs correlation tracking for each velocity group which is grouped by the velocity grouping unit.
摘要翻译： 本发明包括发送/接收基于FMCW的扫描信号的发射机/接收机20，速度分组单元36，其基于来自发射机/接收机20的扫描信号计算出的目标的速度对每个速度范围进行目标的分组。 接收机以及对由速度分组单元分组的每个速度组进行相关跟踪的相关跟踪单元37。
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3.发明申请Substrate with light-shielding film, color filter substrate, method of manufacture of both, and display device having substrate with light-shielding film 审中-公开具有遮光膜的基板，滤色器基板，两者的制造方法以及具有带有遮光膜的基板的显示装置公开(公告)号：US20070026324A1
公开(公告)日：2007-02-01
申请号：US11484606
申请日：2006-07-12
CPC分类号： C23F1/26 , C03C17/36 , C03C17/3618 , C03C17/3649 , C03C17/3657 , C03C17/3671 , C03C2217/948 , C23C14/0036 , C23C14/083 , C23C14/3492 , G02F1/133512
摘要： A substrate with a light-shielding film according to one mode of the invention is obtained in a method of manufacture of a substrate with a light-shielding film having a light-shielding film pattern formed on a substrate, by depositing in order a first film having chromium oxide and a second film having chromium on a substrate, to form a multilayer film; forming a resist pattern on the multilayer film; performing etching of the multilayer film, using an etching liquid comprising ceric ammonium nitrate to which nitric acid is added at a concentration of at least 2.5 mol/liter, to form a light-shielding film pattern; and removing the resist pattern.
摘要翻译： 根据本发明的一种模式的具有遮光膜的基板是在具有通过在基板上形成的遮光膜图案的遮光膜的基板的制造方法中获得的，通过依次沉积第一膜 具有氧化铬和在基板上具有铬的第二膜，以形成多层膜; 在所述多层膜上形成抗蚀剂图案; 使用包含浓度为2.5摩尔/升的硝酸的硝酸铈铵的蚀刻液进行多层膜的蚀刻，形成遮光膜图案; 并去除抗蚀剂图案。
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公开(公告)号：US20060267120A1
公开(公告)日：2006-11-30
申请号：US11364195
申请日：2006-03-01
IPC分类号： H01L29/82
CPC分类号： G02F1/133555 , G02F1/133371 , G02F1/136227
摘要： A liquid crystal apparatus includes a TFT array substrate which includes gate wirings having a gate electrode, source wirings having a source electrode, a thin film transistor having the gate electrode, a semiconductor layer, the source electrode, and a drain electrode, an interlayer insulating film provided above the thin film transistor and the gate and source wirings, a transparent pixel electrode having a first transparent conductive film connected to the drain electrode through a contact hole, and put into contact with a surface of a insulating substrate through a pixel opening provided in a gate insulating film and the interlayer insulating film, a reflective pixel electrode made of an Al-alloy connected to the drain electrode, and a second transparent conductive film formed on the reflective electrode. The second transparent conductive film has a same pattern shape as the reflective pixel electrode and a thickness thereof is at least 5 nm.
摘要翻译： 液晶装置包括TFT阵列基板，其包括具有栅电极的栅极布线，具有源电极的源极布线，具有栅电极的薄膜晶体管，半导体层，源电极和漏电极，层间绝缘 设置在薄膜晶体管上方的薄膜晶体管和栅极和源极布线的透明像素电极，具有通过接触孔连接到漏极的第一透明导电膜的透明像素电极，并通过设置在像素开口处的像素开口与绝缘基板的表面接触 在栅极绝缘膜和层间绝缘膜中，由连接到漏电极的Al合金制成的反射像素电极和形成在反射电极上的第二透明导电膜。 第二透明导电膜具有与反射像素电极相同的图案形状，并且其厚度为至少5nm。
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公开(公告)号：US07031197B2
公开(公告)日：2006-04-18
申请号：US10849241
申请日：2004-05-20
申请人： Takuji Yoshida
发明人： Takuji Yoshida
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/12 , H01L27/115
摘要： An electrically erasable programmable read-only memory receives a single supply voltage and a ground voltage, and generates a first voltage higher than both the supply voltage and the ground voltage, and a second voltage lower than both the supply voltage and the ground voltage. Each memory cell in the memory has a nonvolatile storage transistor with a floating gate. To erase the memory cell, the first voltage is applied on a first side of the floating gate and th second voltage is on a second, opposite side of the floating gate. To program the memory cell, the second voltage is applied on the first side of the floating gate, and the first voltage is applied on the second side of the floating gate.
摘要翻译： 电可擦除可编程只读存储器接收单个电源电压和接地电压，并且产生比电源电压和接地电压高的第一电压，以及低于电源电压和接地电压两者的第二电压。 存储器中的每个存储单元具有带有浮动栅极的非易失性存储晶体管。 为了擦除存储单元，第一电压施加在浮置栅极的第一侧上，第二电压在浮置栅极的第二相对侧上。 为了对存储单元进行编程，第二电压施加在浮置栅极的第一侧上，并且第一电压施加在浮动栅极的第二侧上。
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公开(公告)号：US06660718B1
公开(公告)日：2003-12-09
申请号：US09980113
申请日：2001-11-30
IPC分类号： C07H1708
CPC分类号： C07H17/08
摘要： A compound represented by the following general formula (I) or a salt thereof: wherein R&agr; represents a C1-C10 alkyl group, a C3-C10 alkenyl group, a C7-C15 aralkyl group, a quinolinylalkyl group, a quinolinylalkenyl group, a C2-C10 alkylcarbonyl group, a C7-C15 aralkylcarbonyl group, a C4-C7 cycloalkylcarbonyl group, benzoyl group, an imidazolylcarbonyl group and the like; R1 represents hydrogen atom, a C1-C10 alkyl group, or a C2-C10 alkylcarbonyl group; and R2 represents hydrogen atom, a C1-C10 alkyl group, or a C2-C10 alkylcarbonyl group, provided that the compound wherein R&agr; represents a C2-C10 alkylcarbonyl group and both of R1 and R2 represent a C1-C10 alkyl group is excluded.
摘要翻译： 由以下通式（I）表示的化合物或其盐：其中R表示C1-C10烷基，C3-C10烯基，C7-C15芳烷基，喹啉基烷基，喹啉基烯基 C2-C10烷基羰基，C7-C15芳烷基羰基，C4-C7环烷基羰基，苯甲酰基，咪唑基羰基等; R 1表示氢原子，C 1 -C 10烷基或C 2 -C 10烷基羰基; 并且R 2表示氢原子，C 1 -C 10烷基或C 2 -C 10烷基羰基，条件是其中R 1表示C 2 -C 10烷基羰基并且R 1和R 2均为 2>表示不包括C1-C10烷基。
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公开(公告)号：US5267209A
公开(公告)日：1993-11-30
申请号：US757927
申请日：1991-09-12
申请人： Takuji Yoshida
发明人： Takuji Yoshida
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/12 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/16 , G11C16/12 , H01L27/115
摘要： An electrically erasable programmable read-only memory receives a single supply voltage and a ground voltage, and generates a first voltage higher than both the supply voltage and the ground voltage, and a second voltage lower than both the supply voltage and the ground voltage. Each memory cell in the memory has a nonvolatile storage transistor with a floating gate. To erase the memory cell, the first voltage is applied on a first side of the floating gate and second voltage is applied on a second, opposite side of the floating gate. To program the memory cell, the second voltage is applied on the first side of the floating gate, and the first voltage is applied on the second side of the floating gate.
摘要翻译： 电可擦除可编程只读存储器接收单个电源电压和接地电压，并且产生比电源电压和接地电压高的第一电压，以及低于电源电压和接地电压两者的第二电压。 存储器中的每个存储单元具有带有浮动栅极的非易失性存储晶体管。 为了擦除存储单元，第一电压施加在浮置栅极的第一侧上，而第二电压施加在浮置栅极的第二相对侧上。 为了对存储单元进行编程，第二电压施加在浮置栅极的第一侧上，并且第一电压施加在浮动栅极的第二侧上。
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8.发明授权公开(公告)号：US07733446B2
公开(公告)日：2010-06-08
申请号：US11093223
申请日：2005-03-30
IPC分类号： G02F1/136 , G02F1/1335
CPC分类号： G02F1/13458 , G02F1/133555 , G02F1/13439 , G02F1/136227
摘要： The present invention intends to provide a manufacturing method of a semi-transmissive liquid crystal display device in which method a structure and manufacturing process thereof are simplified to enable to reduce the manufacturing cost. In order to achieve the above object, a semi-transmissive liquid crystal display device in the invention has a layer constitution in which a reflective pixel electrode is formed with a second conductive film that constitutes a source electrode, a drain electrode, a source wiring and so on and on an upper layer of the second metal film a transmissive pixel electrode made of a transparent conductive film is formed through the insulating film. A TFT array substrate can be formed through 5 times of photoengraving process.
摘要翻译： 本发明旨在提供一种半透射型液晶显示装置的制造方法，其中简化了其结构和制造方法的方法，从而能够降低制造成本。 为了实现上述目的，本发明的半透射型液晶显示装置具有：反射像素电极形成有构成源电极，漏电极，源极配线的第二导电膜的层结构， 因此在第二金属膜的上层上，通过绝缘膜形成由透明导电膜构成的透射性像素电极。 可以通过5倍的光刻工艺形成TFT阵列基板。
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公开(公告)号：US20080118996A1
公开(公告)日：2008-05-22
申请号：US11951832
申请日：2007-12-06
申请人： Nobuaki Ishiga , Takuji Yoshida , Yuichi Masutani , Shingo Nagano
发明人： Nobuaki Ishiga , Takuji Yoshida , Yuichi Masutani , Shingo Nagano
IPC分类号： H01L21/28
CPC分类号： G02F1/136227 , G02F1/133555 , G02F2001/136236 , H01L21/32139 , H01L27/124
摘要： A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.
摘要翻译： 一种制造薄膜晶体管阵列基板的方法，该薄膜晶体管阵列基板包括绝缘基板，具有连接到漏电极的像素电极的显示像素，栅极布线和垂直于栅极布线的源极布线，包括形成第一薄金属多 其上层包括铝，并铺展光致抗蚀剂，在与第二薄金属膜连接的区域中形成光刻胶的厚度小于其它区域，图案化第一薄金属膜，减少 去除该区域中的光致抗蚀剂，去除该区域中的上层以暴露下层，形成层间绝缘膜并将其图案化以暴露该区域中的下层，并将该图案化 第二薄金属膜包括该区域，以将下层连接到第二薄金属膜。
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公开(公告)号：US07352421B2
公开(公告)日：2008-04-01
申请号：US11364195
申请日：2006-03-01
IPC分类号： G02F1/1335
CPC分类号： G02F1/133555 , G02F1/133371 , G02F1/136227
摘要： A liquid crystal apparatus includes a TFT array substrate which includes gate wirings having a gate electrode, source wirings having a source electrode, a thin film transistor having the gate electrode, a semiconductor layer, the source electrode, and a drain electrode, an interlayer insulating film provided above the thin film transistor and the gate and source wirings, a transparent pixel electrode having a first transparent conductive film connected to the drain electrode through a contact hole, and put into contact with a surface of a insulating substrate through a pixel opening provided in a gate insulating film and the interlayer insulating film, a reflective pixel electrode made of an Al-alloy connected to the drain electrode, and a second transparent conductive film formed on the reflective electrode. The second transparent conductive film has a same pattern shape as the reflective pixel electrode and a thickness thereof is at least 5 nm.
摘要翻译： 液晶装置包括TFT阵列基板，其包括具有栅电极的栅极布线，具有源电极的源极布线，具有栅电极的薄膜晶体管，半导体层，源电极和漏电极，层间绝缘 设置在薄膜晶体管上方的薄膜晶体管和栅极和源极布线的透明像素电极，具有通过接触孔连接到漏极的第一透明导电膜的透明像素电极，并通过设置在像素开口处的像素开口与绝缘基板的表面接触 在栅极绝缘膜和层间绝缘膜中，由连接到漏电极的Al合金制成的反射像素电极和形成在反射电极上的第二透明导电膜。 第二透明导电膜具有与反射像素电极相同的图案形状，并且其厚度为至少5nm。
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