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9 条记录 (耗时 0.078 秒)

    INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP
    2.
    发明申请
    INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP 有权
    集成电路芯片，减少红外线

    公开(公告)号：US20100276805A1

    公开(公告)日：2010-11-04

    申请号：US12435398

    申请日：2009-05-04

    申请人： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

    发明人： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

    IPC分类号： H01L23/522

    CPC分类号： H01L23/5286 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

    摘要翻译： 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。

    Method of reducing current leakage in a metal insulator metal semiconductor capacitor and semiconductor capacitor thereof
    4.
    发明授权
    Method of reducing current leakage in a metal insulator metal semiconductor capacitor and semiconductor capacitor thereof 有权
    减少金属绝缘体金属半导体电容器及其半导体电容器中漏电的方法

    公开(公告)号：US07678659B2

    公开(公告)日：2010-03-16

    申请号：US11421771

    申请日：2006-06-02

    申请人： Chao-Chun Tu ,  Ming-Chieh Lin

    发明人： Chao-Chun Tu ,  Ming-Chieh Lin

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76816 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

    摘要翻译： 一种用于减小半导体电容器中的漏电流的方法。 该方法包括提供用于收集电荷的顶板，提供用于收集与顶板相反的电荷的底板，提供用于在顶板和底板之间绝缘的介电层，提供顶部接触，提供底部接触， 提供多个通孔，包括用于将顶板连接到顶部触点的顶部通孔，以及用于将底板连接到底部触点的底部通孔; 以及分离通孔和相邻结构，使得它们的距离大于制造半导体电容器的半导体工艺的铸造设计规则的最小经过间隔要求。

    METHOD OF REDUCING CURRENT LEAKAGE IN A METAL INSULATOR METAL SEMICONDUCTOR CAPACITOR AND SEMICONDUCTOR CAPACITOR THEREOF
    5.
    发明申请
    METHOD OF REDUCING CURRENT LEAKAGE IN A METAL INSULATOR METAL SEMICONDUCTOR CAPACITOR AND SEMICONDUCTOR CAPACITOR THEREOF 有权
    金属绝缘子金属半导体电容器及其半导体电容器中减少电流泄漏的方法

    公开(公告)号：US20070072361A1

    公开(公告)日：2007-03-29

    申请号：US11421771

    申请日：2006-06-02

    申请人： Chao-Chun Tu ,  Ming-Chieh Lin

    发明人： Chao-Chun Tu ,  Ming-Chieh Lin

    IPC分类号： H01L21/8242 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

    CPC分类号： H01L21/76816 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

    摘要翻译： 一种用于减小半导体电容器中的漏电流的方法。 该方法包括提供用于收集电荷的顶板，提供用于收集与顶板相反的电荷的底板，提供用于在顶板和底板之间绝缘的介电层，提供顶部接触，提供底部接触， 提供多个通孔，包括用于将顶板连接到顶部触点的顶部通孔，以及用于将底板连接到底部触点的底部通孔; 以及分离通孔和相邻结构，使得它们的距离大于制造半导体电容器的半导体工艺的铸造设计规则的最小经过间隔要求。

    Integrated circuit chip with reduced IR drop
    6.
    发明授权
    Integrated circuit chip with reduced IR drop 有权
    集成电路芯片具有降低的IR降

    公开(公告)号：US08476745B2

    公开(公告)日：2013-07-02

    申请号：US12435398

    申请日：2009-05-04

    申请人： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

    发明人： Chao-Chun Tu ,  Shih-Hung Lin ,  Chih-Chien Huang ,  Tien-Chang Chang

    IPC分类号： H01L23/495

    CPC分类号： H01L23/5286 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.

    摘要翻译： 集成电路芯片包括半导体衬底; 第一互连线，其具有在所述半导体衬底上的第一部分和第二部分，其中所述第二部分与所述第一部分分离; 位于所述第一互连线下方的第二互连线; 第一导电通孔，电连接第一部分与第二互连线; 位于第一互连线和第二互连线之间的导电层; 以及将导电层与第二部分电耦合的第二导电通孔。