公开(公告)号：US20120147561A1

公开(公告)日：2012-06-14

申请号：US13401282

申请日：2012-02-21

申请人： Taqing Feng ,  Xiaoming Kong ,  Hongliang Chen ,  Zhijian Li ,  Liqian Zhai ,  Qiong Wu

发明人： Taqing Feng ,  Xiaoming Kong ,  Hongliang Chen ,  Zhijian Li ,  Liqian Zhai ,  Qiong Wu

IPC分类号： H05K7/20 ,  F28F13/00 ,  F28D15/04

CPC分类号： H05K7/2029 ,  H05K7/20681

摘要： Embodiments of the present invention disclose a heat dissipation device, including: a closed shell and a temperature control device. The temperature control device includes: a cold storage medium module, a first group of thermosiphons, and a second group thermosiphons; wherein the cold storage medium module is disposed at the outside of the closed shell, the first group thermosiphons are provided with a first group of evaporation ends and a first group of condensation ends, and the second group of thermosiphons are provided with a second group of evaporation ends and a second group of condensation ends. Embodiments of the present invention also disclose a communication device and a heat dissipation method for a communication device. The above technical solutions save electric energy and improve the effects of energy saving and emission reduction of the system.

摘要翻译： 本发明的实施例公开了一种散热装置，包括：封闭壳体和温度控制装置。 温度控制装置包括：冷藏介质模块，第一组热虹吸管和第二组热虹吸管; 其中所述冷藏介质模块设置在所述封闭壳体的外部，所述第一组热虹吸管设置有第一组蒸发端和第一组冷凝端，并且所述第二组热虹吸管设置有第二组 蒸发端和第二组冷凝结束。 本发明的实施例还公开了一种用于通信设备的通信设备和散热方法。 以上技术方案节省电能，提高系统节能减排的效果。

公开(公告)号：US08638248B2

公开(公告)日：2014-01-28

申请号：US13269495

申请日：2011-10-07

申请人： Qiong Wu ,  Kevin Mahooti

发明人： Qiong Wu ,  Kevin Mahooti

IPC分类号： H03M1/06

CPC分类号： H03M1/1047 ,  H03M1/1052 ,  H03M1/462 ,  H03M1/468

摘要： A method and apparatus for correcting the offset and linearity error of a data acquisition system. A charge redistribution digital to analog convertor (CDAC) is connected to one of the differential inputs of a comparator whose second input comes from a function CDAC. The calibration algorithm is built into a digital control unit. The digital control unit detects the offset and capacitor mismatch errors sequentially, stores the calibration codes for each error in calibration mode and provides the input-dependent error correction signals synchronized with the binary search timing to adjust the differential input of the comparator and compensate the input-dependent errors present at the output of the non-ideal function CDAC during normal conversions.

摘要翻译： 一种用于校正数据采集系统的偏移和线性误差的方法和装置。 电荷再分配数字到模拟转换器（CDAC）连接到比较器的一个差分输入端，其比较器的第二输入来自功能CDAC。 校准算法内置在数字控制单元中。 数字控制单元依次检测偏移和电容器失配误差，将每个误差的校准码存储在校准模式中，并提供与二进制搜索定时同步的输入相关误差校正信号，以调整比较器的差分输入并补偿输入 在正常转换期间，非理想函数CDAC的输出存在相关误差。

公开(公告)号：US20130194115A1

公开(公告)日：2013-08-01

申请号：US13363255

申请日：2012-01-31

申请人： Qiong Wu ,  Kevin Mahooti ,  Qinghai Hu

发明人： Qiong Wu ,  Kevin Mahooti ,  Qinghai Hu

IPC分类号： H03M1/12 ,  H03M1/66

CPC分类号： H03M1/144 ,  H03M1/069 ,  H03M1/46

摘要： An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

摘要翻译： 一种设备实现模数转换，具有对参考建立误差的释放要求，并提高了对源自电源，接地和正负参考的噪声的抗扰度。 它包括比较指定参考电平与模拟输入，多DAC子电路和单独的非二进制搜索方案，以及控制参考搜索过程的数字控制逻辑。 不同的非二进制搜索算法之间不会发生串扰。 每个冗余方案被定位在相应的DAC子电路中，并且仅在当前DAC中覆盖参考电平。 非二进制搜索算法在数字域中实现，并且将非二进制搜索步长与搜索步骤的数量进行交换，以将冗余引入参考级。

公开(公告)号：US20110148473A1

公开(公告)日：2011-06-23

申请号：US12645346

申请日：2009-12-22

申请人： Qiong Wu ,  Kevin Mahooti

发明人： Qiong Wu ,  Kevin Mahooti

IPC分类号： G11C27/02

CPC分类号： G11C27/024

摘要： An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

公开(公告)号：US06459738B1

公开(公告)日：2002-10-01

申请号：US09494105

申请日：2000-01-28

申请人： Qiong Wu ,  Kwok K. Chau ,  Toshiaki Yoshino

发明人： Qiong Wu ,  Kwok K. Chau ,  Toshiaki Yoshino

IPC分类号： H04N712

CPC分类号： H04N19/423 ,  H04N19/61

摘要： A decoder for decoding a compressed incoming interruptible bitstream is disclosed. The decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.

摘要翻译： 公开了一种用于解码压缩输入可中断比特流的解码器。 解码器包括能够接收锁存命令的输入寄存器，并且还能够在接收到锁存命令时在特定状态下锁存存储的数据。 解码器还包括与输入寄存器通信的诸如可变长度解码逻辑或游程长度解码逻辑的解码逻辑。 进一步包括在解码器中的是与解码逻辑通信的输出寄存器，其也能够接收锁存命令，并且还能够在接收到锁存命令时在特定状态下锁存存储的数据。 最后，解码器包括与输入寄存器和输出寄存器通信的寄存器控制器。 寄存器控制器能够从系统接收到停止命令，并且在接收到停止命令时，寄存器控制器将锁存命令发送到输入寄存器和输出寄存器。

公开(公告)号：USD1041269S1

公开(公告)日：2024-09-10

申请号：US29872139

申请日：2023-03-07

申请人： Qiong Wu

设计人： Qiong Wu

摘要： FIG. 1 is a front elevation view of a shaker cup bar tool stand showing the new design;
FIG. 2 is a back elevation view thereof;
FIG. 3 is a left-side view thereof;
FIG. 4 is a right-side view thereof;
FIG. 5 is a top plan view thereof;
FIG. 6 is a bottom plan view thereof;
FIG. 7 is a perspective view thereof;
FIG. 8 is a perspective view thereof; and,
FIG. 9 is a perspective view thereof.
The broken lines depict portions of the article that form no part of the claimed design.

公开(公告)号：US09075103B2

公开(公告)日：2015-07-07

申请号：US13645789

申请日：2012-10-05

申请人： Qiong Wu ,  Chien-Ming Lan

发明人： Qiong Wu ,  Chien-Ming Lan

IPC分类号： G01R31/28 ,  G01R35/00 ,  G01R1/073

CPC分类号： G01R31/2831 ,  G01R1/07307 ,  G01R35/00

摘要： Provided is a test structure for wafer acceptance test (WAT). The test structure includes a row of a plurality of first pads electrically connecting to each other, a second pad, a third pad, a first peripheral metal line, and a second peripheral metal line. The second pad is disposed in the vicinity of a first end of the row, wherein the second pad is electrically disconnected to the first pads. The third pad is disposed in the vicinity of a second end of the row, wherein the third pad is electrically disconnected to the first pads. The first peripheral metal line is disposed at a first side of the row and electrically connected to the second pad. The second peripheral metal line is disposed at a second side of the row and electrically connected to the third pad.

摘要翻译： 提供了用于晶片验收测试（WAT）的测试结构。 测试结构包括一排彼此电连接的多个第一焊盘，第二焊盘，第三焊盘，第一外围金属线和第二外围金属线。 第二焊盘设置在该行的第一端附近，其中第二焊盘与第一焊盘电断开。 第三焊盘设置在行的第二端附近，其中第三焊盘与第一焊盘电连接。 第一外围金属线设置在行的第一侧并电连接到第二焊盘。 第二周边金属线设置在行的第二侧并电连接到第三焊盘。

公开(公告)号：US08546125B2

公开(公告)日：2013-10-01

申请号：US13031350

申请日：2011-02-21

申请人： Guo-Qiang Chen ,  Zheng-Jun Li ,  Zhen-Yu Shi ,  Ying-Ying Guo ,  Jia Jian ,  Qiong Wu

发明人： Guo-Qiang Chen ,  Zheng-Jun Li ,  Zhen-Yu Shi ,  Ying-Ying Guo ,  Jia Jian ,  Qiong Wu

IPC分类号： C12N1/20 ,  C12P9/00 ,  C07H21/04

CPC分类号： C12N9/88 ,  C12N9/0006 ,  C12N9/0008 ,  C12N9/1029 ,  C12P7/625 ,  C12Y101/01036 ,  C12Y101/01061 ,  C12Y102/01016 ,  C12Y203/01009 ,  C12Y203/01016 ,  C12Y401/01001

摘要： Known attempts using engineered bacteria to produce P(3HB-co-4HB) with carbon sources that are structurally unrelated to 4-hydroxybutyrate resulted in relatively low 4HB monomer content of 1.5 to 5 mol %. The current invention provides recombinant hosts for producing P(3HB-co-4HB) wherein the plasmid including succinate semialdehyde dehydrogenase gene (sucD gene) and 4-hydroxybutyrate dehydrogenase gene (4hbD gene) further includes pyruvate decarboxylase promoter (Ppdc). It was found that the 4HB monomer content in P(3HB-co-4HB) is significantly enhanced to be over 20 mol %, in the range of 8.8 to 23 mol %.

摘要翻译： 使用工程细菌产生具有与4-羟基丁酸盐结构无关的碳源的P（3HB-co-4HB）的已知尝试导致相对较低的4HB单体含量为1.5至5mol％。 本发明提供了用于产生P（3HB-co-4HB）的重组宿主，其中包含琥珀酸半醛脱氢酶基因（sucD基因）和4-羟基丁酸脱氢酶基因（4hbD基因）的质粒还包括丙酮酸脱羧酶启动子（Ppdc）。 发现P（3HB-co-4HB）中的4HB单体含量显着提高到超过20mol％，在8.8至23mol％的范围内。

公开(公告)号：US20110148507A1

公开(公告)日：2011-06-23

申请号：US12645298

申请日：2009-12-22

申请人： Qiong Wu ,  Kevin Mahooti

发明人： Qiong Wu ,  Kevin Mahooti

IPC分类号： H03K17/687

CPC分类号： H03K17/162 ,  G11C27/024

摘要： A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs.

摘要翻译： 采样和保持馈电开关具有并联PMOS分支和并联NMOS分支，每个分支从输入节点延伸到连接到保持电容器的输出节点。 每个PMOS分支具有连接到匹配的PMOS虚拟FET的PMOS开关FET，并且每个NMOS分支具有连接到匹配的NMOS虚拟FET的NMOS开关FET。 采样时钟打开和关闭PMOS开关FET，同步反相采样时钟实现PMOS虚拟FET的互补开关切换。 同时，同步反相采样时钟导通和关断NMOS开关FET，采样时钟影响NMOS虚拟FET的互补开 - 关切换。 偏置顺控器电路以互补的方式偏置PMOS开关FET的主体和PMOS虚拟FET的主体，并且也以互补的方式偏置NMOS开关FET和NMOS虚拟FET。 PMOS伪FET的开 - 关切换注入电荷，消除PMOS信号开关FET的电荷注入，并且注入由PMOS信号开关FET注入的毛刺消除毛刺。 NMOS虚拟FET的开 - 关切换注入由NMOS信号开关FET取消电荷注入的电荷，并注入消除由NMOS信号开关FET注入的毛刺的毛刺。

公开(公告)号：US20110133816A1

公开(公告)日：2011-06-09

申请号：US12630662

申请日：2009-12-03

申请人： Qiong Wu ,  Kevin Mahooti

发明人： Qiong Wu ,  Kevin Mahooti

IPC分类号： H03K17/687

CPC分类号： H03K17/164

摘要： An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.

摘要翻译： 模拟采样保持开关具有从输入节点延伸到连接到保持电容器的输出节点的并行分支，每个分支具有与PMOS伪FET串联的PMOS信号开关FET。 采样时钟控制PMOS信号开关FET的导通截止切换，并且采样时钟的反相控制PMOS虚拟FET的互补开 - 关切换。 偏置顺序器电路以PMOS互补方式偏置PMOS信号开关FET并且以与它们各自的开关状态同步的方式偏置PMOS虚拟FET。 PMOS伪FET的开 - 关切换由PMOS信号开关FET注入电荷消除电荷注入，并且注入消除由PMOS信号开关FET注入的毛刺的毛刺。