公开(公告)号：US3958268A

公开(公告)日：1976-05-18

申请号：US466850

申请日：1974-05-03

申请人： Tatsuya Kamei ,  Yoshikazu Hosokawa

发明人： Tatsuya Kamei ,  Yoshikazu Hosokawa

IPC分类号： H01L29/74 ,  H01L29/749

CPC分类号： H01L29/749 ,  H01L29/7436

摘要： A thyristor highly proof against dv/dt in which to prevent malignition due to the displacement current produced by the application of an abruptly rising forward voltage or the internal leakage current increasing with the temperature rise of the semiconductor substrate, an auxiliary electrode is provided to the intermediate region adjacent to one of the outermost regions of the semiconductor substrate to which two main electrodes, anode and cathode, are provided, the auxiliary electrode and the main electrode on the one outermost region being connected electrically, and a control region having the opposite conductivity type to that of the intermediate region is formed in the intermediate region between the auxiliary electrode and the main electrode on the one outermost region, the control region being provided with a gate electrode. By supplying a control signal to the gate electrode a depletion layer is produced in the intermediate region such that the path of the control signal from the gate electrode to the auxiliary electrode is completely blocked and the control signal is all utilized for the ignition. The displacement current and the leakage current are bypassed from the auxiliary electrode to the main electrode on the one outermost region.

公开(公告)号：US4063115A

公开(公告)日：1977-12-13

申请号：US720492

申请日：1976-09-03

申请人： Shinzi Okuhara ,  Yoshikazu Hosokawa ,  Tatsuya Kamei ,  Masayoshi Suzuki

发明人： Shinzi Okuhara ,  Yoshikazu Hosokawa ,  Tatsuya Kamei ,  Masayoshi Suzuki

IPC分类号： H02M1/08 ,  H03K17/082 ,  H03K17/73 ,  H03K17/72

CPC分类号： H03K17/73 ,  H03K17/0824

摘要： A semiconductor switch assuring the easy formation of a semiconductor integrated circuit and having high control sensitivity while maintaining high dv/dt - immunity, which comprises a PNPN switch of an equivalently four-layered structure including at least three PN-junctions, an anode and a cathode, switching means including a control terminal and connected with the PNPN switch to shunt one of the three PN-junctions at either one end of the PNPN switch, amplifying means, and a capacitive element for differentiating a voltage applied between the anode and the cathode of the PNPN switch to allow a current to flow into the control terminal of the switching means through the amplifying means, so that the switching means is driven by the current thereby to short-circuit the one of three PN-junctions.

摘要翻译： 半导体开关确保容易地形成半导体集成电路并且具有高的控制灵敏度，同时保持高的dv / dt-抗扰度，其包括具有至少三个PN结的等效四层结构的PNPN开关，阳极和 阴极，包括控制端并与PNPN开关连接的开关装置，以分流PNPN开关的任一端的三个PN结中的一个，放大装置和用于区分施加在阳极和阴极之间的电压的电容元件 的PNPN开关以允许电流通过放大装置流入开关装置的控制端，使得开关装置由电流驱动，从而使三个PN结中的一个短路。

公开(公告)号：US5049967A

公开(公告)日：1991-09-17

申请号：US631907

申请日：1990-12-21

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US3943550A

公开(公告)日：1976-03-09

申请号：US534373

申请日：1974-12-19

申请人： Nobutake Konishi ,  Tsutomu Yatsuo ,  Tatsuya Kamei ,  Masahiro Okamura ,  Takuzo Ogawa

发明人： Nobutake Konishi ,  Tsutomu Yatsuo ,  Tatsuya Kamei ,  Masahiro Okamura ,  Takuzo Ogawa

IPC分类号： H01L31/111 ,  H01L29/74

CPC分类号： H01L31/1113

摘要： A light-activated semiconductor-controlled rectifier device comprising four layers of PNPN is disclosed in which a part of the edges of the PN junction formed between the intermediate P-type layer and the intermediate N-type layer is exposed on the same side on which the outer P-type layer is exposed, so that a photo-trigger signal is radiated on that exposed part of the edges of the PN junction.

摘要翻译： 公开了一种包括四层PNPN的光激活半导体控制整流器件，其中形成在中间P型层和中间N型层之间的PN结的边缘的一部分暴露在同一侧上， 暴露外部P型层，使得在PN结的边缘的暴露部分上照射触发信号。

公开(公告)号：US08108660B2

公开(公告)日：2012-01-31

申请号：US12358233

申请日：2009-01-22

申请人： Hironori Kasahara ,  Keiji Kimura ,  Masayuki Ito ,  Tatsuya Kamei ,  Toshihiro Hattori

发明人： Hironori Kasahara ,  Keiji Kimura ,  Masayuki Ito ,  Tatsuya Kamei ,  Toshihiro Hattori

IPC分类号： G06F1/04

CPC分类号： G06F15/16

摘要： Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.

摘要翻译： 每个处理器都有一个屏障写入寄存器和一个屏障读取寄存器。 每个屏障写入寄存器通过专用接线块连接到每个屏障读取寄存器。 例如，处理器的1位屏障写入寄存器经由布线块连接到处理器中包含的每个8位屏障读取寄存器的第一位，而另一个处理器的1位屏障写入寄存器是 通过接线块连接到处理器中包含的每个8位屏障读取寄存器的第二位。 例如，处理器将信息写入其自己的屏障写入寄存器，从而通知其他处理器的同步待机并读取其自己的障碍读取寄存器，从而识别其他处理器是否处于同步待机状态。 因此，沿着屏障同步处理不需要特殊的专用指令，并且可以高速进行处理。

公开(公告)号：US20050257011A1

公开(公告)日：2005-11-17

申请号：US10520653

申请日：2002-09-30

申请人： Yuki Kondoh ,  Tatsuya Kamei ,  Makoto Ishikawa

发明人： Yuki Kondoh ,  Tatsuya Kamei ,  Makoto Ishikawa

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0888

摘要： A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.

摘要翻译： 半导体数据处理器具有构成高速缓冲存储器的第一存储器（6），能够由第一存储器构成可高速缓存区域或不可缓存区域的第二存储器（20），以及能够执行 当第二存储器被读取访问作为不可缓存区域时，用于输出与读访问相对应的数据的操作。 用于第二存储器的可缓存区域和不可缓存区域的指定由第二存储器映射到的存储器空间的可缓存区域或不可缓存区域的指定来确定。 该指定可以在数据处理器的操作模式下执行，或者例如设置控制寄存器。

公开(公告)号：US4419685A

公开(公告)日：1983-12-06

申请号：US245510

申请日：1981-03-19

申请人： Yoshitaka Sugawara ,  Tatsuya Kamei ,  Tetsuma Sakurai

发明人： Yoshitaka Sugawara ,  Tatsuya Kamei ,  Tetsuma Sakurai

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/735

CPC分类号： H01L29/402 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/735

摘要： A lateral transistor having a high breakdown voltage and operable with an improved current amplification factor and an improved cut-off frequency comprises in a semiconductor substrate of one conductivity type, a base layer of the one conductivity type and an emitter layer of the other conductivity type formed in the base layer. A first collector layer of the other conductivity type is formed in the one principal surface of the substrate apart from the base layer and a second collector layer of the same conductivity type having an impurity concentration lower than that of the first collector layer is formed between the first collector layer and the base layer in contact with the latter layers. Emitter, base and collector electrodes make ohmic contact with the emitter, base and first collector layers respectively. The emitter electrode extends on a passivation film covering the one principal surface of the substrate to terminate at a point on the second collector layer.

摘要翻译： 具有高击穿电压并且具有改善的电流放大因子和改进的截止频率的横向晶体管包括在一种导电类型的半导体衬底中，一种导电类型的基极层和另一种导电类型的发射极层 形成在基层。 另外导电型的第一集电体层形成在与基底层相隔的基板的一个主表面上，并且在第二集电极层之间形成具有比第一集电体层低的杂质浓度的相同导电类型的第二集电极层 第一集电体层和与后一层接触的基层。 发射极，基极和集电极电极分别与发射极，基极和第一集电极层欧姆接触。 发射电极在覆盖衬底的一个主表面的钝化膜上延伸以终止于第二集电极层上的一点。

公开(公告)号：US4058821A

公开(公告)日：1977-11-15

申请号：US668404

申请日：1976-03-19

申请人： Tadahiko Miyoshi ,  Yasutoshi Kurihara ,  Tatsuya Kamei ,  Takuzo Ogawa

发明人： Tadahiko Miyoshi ,  Yasutoshi Kurihara ,  Tatsuya Kamei ,  Takuzo Ogawa

IPC分类号： H01L31/12 ,  H01L31/0232 ,  H01L31/167

CPC分类号： H01L31/0232 ,  H01L31/167

摘要： A photo-coupler semiconductor device includes a semiconductor light emitter and a semiconductor light detector coupled optically with each other through an optical guide. A portion of the optical guide close to the semiconductor light detector is made of glass. The glass portion of the optical guide is brought into intimate contact with a glass layer which is formed on a light sensitive region of the semiconductor light detector. The intimate contact is made by melting the glass portion on the glass layer.

摘要翻译： 光耦合器半导体器件包括半导体光发射器和通过光导相互光耦合的半导体光检测器。 靠近半导体光检测器的光导体的一部分由玻璃制成。 光导体的玻璃部分与形成在半导体光检测器的光敏区域上的玻璃层紧密接触。 通过熔化玻璃层上的玻璃部分来进行紧密接触。

公开(公告)号：US3967308A

公开(公告)日：1976-06-29

申请号：US451679

申请日：1974-03-15

申请人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Takuzo Ogawa ,  Tomoyuki Tanaka

发明人： Tsutomu Yatsuo ,  Tatsuya Kamei ,  Takuzo Ogawa ,  Tomoyuki Tanaka

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/74 ,  H01L29/747

CPC分类号： H01L29/747 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/42308 ,  H01L29/74

摘要： A thyristor with a gate electrode formed on the side of an anode electrode. An auxiliary region of a large lateral resistance is formed in a surface layer of the substrate between the anode and gate electrodes.

摘要翻译： 具有形成在阳极侧的栅电极的晶闸管。 在阳极和栅电极之间的衬底的表面层中形成有大的横向电阻的辅助区域。

公开(公告)号：US08200934B2

公开(公告)日：2012-06-12

申请号：US11865669

申请日：2007-10-01

申请人： Hironori Kasahara ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

发明人： Hironori Kasahara ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

IPC分类号： G06F12/00

CPC分类号： G06F15/167

摘要： To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.

摘要翻译： 为了减少处理器核心之间的数据传输的开销并提高处理器的处理能力，提供了一种处理器，包括：用于执行计算处理的CPU; 用于存储数据的内部存储器; 以及数据传送单元，用于在内部存储器和共享存储器之间执行数据传送，其中：数据传送单元包括：命令链模块，用于执行由包括数据传送指令的多个命令形成的命令序列; 以及监视器模块，用于读取预先在内部存储器中设置的数据并重复监视数据，直到数据的比较值和值变得彼此相等时，当这样读取的命令序列的多个命令之一是 预定命令 命令链模块在监控模块完成监控后，在命令序列中执行下一个命令。