摘要:
Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be decreased. In a high electron mobility transistor 1, a supporting substrate 3 is composed of AlN, AlGaN, or GaN. An AlyGa1-yN epitaxial layer 5 has a surface roughness (RMS) of 0.25 mm or less, wherein the surface roughness is defined by a square area measuring 1 μm per side. A GaN epitaxial layer 7 is provided between the AlyGa1-yN supporting substrate 3 and the AlyGa1-yN epitaxial layer 5. A Schottky electrode 9 is provided on the AlyGa1-yN epitaxial layer 5. A first ohmic electrode 11 is provided on the AlyGa1-yN epitaxial layer 5. A second ohmic electrode 13 is provided on the AlyGa1-yN epitaxial layer 5. One of the first and second ohmic electrodes 11 and 13 constitutes a source electrode, and the other constitutes a drain electrode. The Schottky electrode 9 constitutes a gate electrode of the high electron mobility transistor 1.
摘要翻译:提供可以减少来自肖特基电极的漏电流的III族氮化物半导体器件。 在高电子迁移率晶体管1中,支撑基板3由AlN,AlGaN或GaN构成。 Al钇1-y N外延层5具有0.25mm或更小的表面粗糙度(RMS),其中表面粗糙度由测量1的正方形面积 妈妈每边。 在AlGaN外延层7之间设置有支撑衬底3的Al 1 Y y-N支撑衬底和Al 1 Al- 在N外延层5上设置肖特基电极9.设置第一欧姆电极11和第一欧姆电极11。 在Al钇1-y N外延层5上。第二欧姆电极13设置在Al钇1 Ga -Y / N外延层5.第一和第二欧姆电极11和13中的一个构成源电极,另一个构成漏电极。 肖特基电极9构成高电子迁移率晶体管1的栅电极。
摘要:
Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.
摘要翻译:提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管(11)设置有由氮化镓构成的支撑基板(13),由第一氮化镓半导体构成的缓冲层(15),由第二氮化镓半导体构成的沟道层(17) 由第三氮化镓半导体构成的半导体层(19)和用于晶体管(11)的电极结构(栅电极(21),源电极(23)和漏电极(25)),带隙 第三氮化镓半导体的第二氮化镓半导体的碳浓度NC2比第二氮化镓半导体的碳浓度小于4×10 17 cm -3以上, 1016厘米-3。
摘要:
Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.
摘要:
Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.
摘要翻译:提供具有其中可以在n型氮化镓衬底上提供具有期望的低载流子浓度的n型氮化镓膜的结构的垂直氮化镓半导体器件的外延衬底。 氮化镓外延膜(65)设置在氮化镓衬底(63)上。 在氮化镓衬底(63)和氮化镓外延膜(65)中设置一个层区(67)。 氮化镓衬底(43)和氮化镓外延膜(65)之间的界面位于层区(67)中。 在层区域(67)中,施主杂质沿着氮化镓衬底(63)到氮化镓外延膜(65)的轴的峰值为1×10 18 cm -3以上。 供体杂质至少是硅或锗。
摘要:
Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.
摘要翻译:提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管11设置有由氮化镓构成的支撑基板13,由第一氮化镓半导体构成的缓冲层15,由第二氮化镓半导体构成的沟道层17,由第三氮化镓半导体构成的半导体层19 氮化镓半导体,以及用于晶体管11的电极结构(栅电极21,源电极23和漏电极25)。第三氮化镓半导体的带隙比第二氮化镓半导体的带隙宽。 第一氮化镓半导体的碳浓度NC1为4×10 17 cm -3以上。 第二氮化镓半导体的碳浓度NC2小于4×10 16 cm -3。
摘要:
Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1−YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1−YN epitaxial layer (O
摘要:
Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1−YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1−YN epitaxial layer (0
摘要:
Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.
摘要:
Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor (11) is provided with a supporting substrate (13) composed of gallium nitride, a buffer layer (15) composed of a first gallium nitride semiconductor, a channel layer (17) composed of a second gallium nitride semiconductor, a semiconductor layer (19) composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode (21), a source electrode (23) and a drain electrode (25)) for the transistor (11). The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.
摘要:
A method for manufacturing a semiconductor device, by which a multiple quantum well structure having a large number of pairs can be efficiently grown while maintaining good crystalline quality, and the semiconductor device, are provided. The semiconductor device manufacturing method of the present invention includes a step of forming a multiple quantum well structure 3 having 50 or more pairs of group III-V compound semiconductor quantum wells. In the step of forming the multiple quantum well structure 3, the multiple quantum well structure is formed by metal-organic vapor phase epitaxy using only metal-organic sources (all metal-organic source MOVPE).