公开(公告)号：US08633096B2

公开(公告)日：2014-01-21

申请号：US12943987

申请日：2010-11-11

申请人： Brian J. Greene ,  Jeffrey B. Johnson ,  Qingqing Liang ,  Edward P. Maciejewski

发明人： Brian J. Greene ,  Jeffrey B. Johnson ,  Qingqing Liang ,  Edward P. Maciejewski

IPC分类号： H01L29/72

CPC分类号： H01L29/66477 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/38 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

公开(公告)号：US20120119294A1

公开(公告)日：2012-05-17

申请号：US12943987

申请日：2010-11-11

申请人： BRIAN J. GREENE ,  Jeffrey B. Johnson ,  Qingqing Liang ,  Edward P. Maciejewski

发明人： BRIAN J. GREENE ,  Jeffrey B. Johnson ,  Qingqing Liang ,  Edward P. Maciejewski

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC分类号： H01L29/66477 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/38 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.

摘要翻译： 一种形成晶体管器件的方法包括：在绝缘体上半导体衬底中注入扩散抑制物质，该衬底包括体衬底，埋层绝缘体层和绝缘体上半导体层，绝缘体上半导体衬底具有一个或 在其上形成更多的栅极结构，使得扩散抑制物质设置在对应于沟道区的绝缘体上半导体层的部分中，并且设置在对应于源极和漏极区的隐埋绝缘体层的部分中。 在源极和漏极区域中引入晶体管掺杂物质。 进行退火以使晶体管掺杂剂物质在基本上垂直的方向上扩散，同时基本上防止晶体管掺杂剂物质进入沟道区域的横向扩散。

公开(公告)号：US07989298B1

公开(公告)日：2011-08-02

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20110183486A1

公开(公告)日：2011-07-28

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20130285211A1

公开(公告)日：2013-10-31

申请号：US13455732

申请日：2012-04-25

申请人： Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

发明人： Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

IPC分类号： H01L29/00 ,  G06F17/50 ,  H01L21/20

CPC分类号： H01L27/1211 ,  G06F17/5068 ,  H01L21/3086 ,  H01L21/845

摘要： Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

摘要翻译： 鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。 构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。 第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。 位于间隙中的是由第二半导体材料构成的层。

公开(公告)号：US08569810B2

公开(公告)日：2013-10-29

申请号：US12961553

申请日：2010-12-07

申请人： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

发明人： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

公开(公告)号：US08536649B2

公开(公告)日：2013-09-17

申请号：US13608860

申请日：2012-09-10

申请人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

发明人： Geng Wang ,  Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries

IPC分类号： H01L29/66

CPC分类号： H01L29/66772 ,  H01L21/2652 ,  H01L29/78696

摘要： The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.

摘要翻译： 本公开提供了一种半导体器件，其可以包括包括覆盖绝缘层的半导体层的衬底。 存在于半导体层的沟道部分上的栅极结构。 第一掺杂区存在于半导体层的沟道部分中，其中第一掺杂区的峰值浓度存在于栅极导体的下部和半导体层的上部之间。 第二掺杂剂区域存在于半导体层的沟道部分中，其中第二掺杂剂区域的峰值浓度存在于半导体层的下部。

公开(公告)号：US08407656B2

公开(公告)日：2013-03-26

申请号：US13167826

申请日：2011-06-24

申请人： Terence B. Hook ,  Jeffrey B. Johnson

发明人： Terence B. Hook ,  Jeffrey B. Johnson

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/544 ,  H01L29/1083 ,  H01L29/7833 ,  H01L2223/5444 ,  H03K3/84

摘要： Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable.

摘要翻译： 公开了由于加剧的随机掺杂剂波动（RDF）而具有相对大的阈值电压（Vt）变化范围的晶体管的设计方法和结构。 通过在一个或多个晶体管组件中使用互补掺杂和/或通过沟道区域和任何晕圈区域之间的横向掺杂剂不均匀性来实现RDF的恶化，从而达到相对较大的Vt变化范围。 还公开了一种用于随机数发生器的设计方法和结构，该方法和结构包括具有如此大的Vt变化的多对基本相同的晶体管，并且其依赖于晶体管对的Vt失配以产生多位输出（例如， 芯片或密钥的唯一标识符）。 通过扩大随机数发生器中的晶体管的Vt变化范围，检测晶体管之间的Vt失配变得更可能，并且所得到的多位输出将更加稳定。

公开(公告)号：US20130015580A1

公开(公告)日：2013-01-17

申请号：US13180842

申请日：2011-07-12

申请人： SAMEER H JAIN ,  Jeffrey B. Johnson ,  Ying Li ,  Hasan M. Nayfeh ,  Ravikumar Ramachandran

发明人： SAMEER H JAIN ,  Jeffrey B. Johnson ,  Ying Li ,  Hasan M. Nayfeh ,  Ravikumar Ramachandran

IPC分类号： H01L29/423 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843

摘要： A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material.

摘要翻译： 提供替代的金属栅极结构及其制造方法。 所述方法包括形成至少一个沟槽结构并在所述至少一个沟槽结构中形成高k电介质材料的衬垫。 该方法还包括调整高k电介质材料的衬垫的高度。 所述方法还包括在所述衬垫上形成至少一个功函数金属，以及在所述至少一个功函数金属和所述高k电介质材料的衬垫上，在所述至少一个沟槽结构中形成金属栅极结构。

公开(公告)号：US08338265B2

公开(公告)日：2012-12-25

申请号：US12269069

申请日：2008-11-12

申请人： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

发明人： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

IPC分类号： H01L21/76

CPC分类号： H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

摘要翻译： 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。