公开(公告)号：US09991350B2

公开(公告)日：2018-06-05

申请号：US15188110

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Yufei Xiong ,  Yunlong Liu ,  Zachary K. Lee ,  Peng Hu

IPC: H01L23/48 ,  H01L29/417 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L21/288 ,  H01L21/285 ,  H01L29/08 ,  H01L29/423 ,  H01L23/485 ,  H01L23/535 ,  H01L21/74 ,  H01L29/06 ,  H01L29/45 ,  H01L29/10

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

公开(公告)号：US20240096814A1

公开(公告)日：2024-03-21

申请号：US17948343

申请日：2022-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Guoyong Zhang ,  She Yu Tang ,  Shu Min Ma ,  Lei Zhang ,  Peng Hu ,  Fei Yu

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: The present disclosure generally relates to semiconductor processing in which an alignment mark is formed. An example is method of semiconductor processing. First and second recesses are formed in a semiconductor substrate. A conformal dielectric layer is formed in the first and second recesses and over the semiconductor substrate. A fill material is formed over the conformal dielectric layer in the first recess and over the conformal dielectric layer in the second recess. The fill material fills at least the first recess over the conformal dielectric layer. The fill material in the first and second recesses is recessed to below a top surface of the conformal dielectric layer. The recessed fill material in the first and second recesses is etched. Exposed portions of the conformal dielectric layer are etched. The second recess including the conformal dielectric layer and the recessed fill material disposed therein forms an alignment mark.

公开(公告)号：US09397180B1

公开(公告)日：2016-07-19

申请号：US14695290

申请日：2015-04-24

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Yufei Xiong ,  Yunlong Liu ,  Zachary K. Lee ,  Peng Hu

IPC: H01L21/00 ,  H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L21/3215 ,  H01L21/265

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

Abstract translation: 一种具有低电阻沉降接触的半导体器件，其中低电阻沉降片接触被蚀刻穿过第一掺杂层并被蚀刻到第二掺杂层中，并且其中第一掺杂层覆盖在第二掺杂层上，并且其中第二掺杂层更重 掺杂了第一掺杂层，并且其中低电阻沉降片接触体填充有金属材料。 一种用于形成具有低电阻沉降接触的半导体器件的方法，其中所述低电阻沉降片接触被蚀刻通过第一掺杂层并且被蚀刻到第二掺杂层中，并且其中所述第一掺杂层覆盖所述第二掺杂层，并且其中所述第二掺杂 所述第一掺杂层更加重掺杂，并且其中所述低电阻沉降片接触体填充有金属材料。