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1.发明申请公开(公告)号：US20110068342A1
公开(公告)日：2011-03-24
申请号：US12563059
申请日：2009-09-18
IPC分类号： H01L29/786 , H01L21/20 , H01L29/04
CPC分类号： H01L21/02532 , H01L21/02587 , H01L21/02675 , H01L27/1285
摘要： A laser method is provided for minimizing variations in transistor threshold voltages. The method supplies a wafer with a laser-crystallized active semiconductor film having a top surface with a first surface roughness. The method laser anneals the active semiconductor film, and in response to the laser annealing, melts the top surface of the active semiconductor film. The result is a top surface with a second roughness, less than the first roughness. More explicitly, the wafer active semiconductor film is crystallized using a laser with a first fluence, and then laser annealed with a second fluence, less than the first fluence. As compared with complementary metal-oxide-semiconductor field-effect (CMOSFET) thin-film transistor (TFT) structures formed in unprocessed regions of the active semiconductor film, the TFT threshold voltage standard deviation for TFTs in laser annealed portions of the active film are 60% less for n-channel and 30% less for p-channel TFTs.
摘要翻译： 提供了一种用于最小化晶体管阈值电压变化的激光方法。 该方法向晶片提供具有第一表面粗糙度的顶表面的激光结晶的有源半导体膜。 该方法激光退火有源半导体膜，并且响应于激光退火，熔化有源半导体膜的顶表面。 结果是具有小于第一粗糙度的第二粗糙度的顶表面。 更明确地说，晶片有源半导体膜使用具有第一注量的激光结晶，然后以小于第一注量的第二注量进行激光退火。 与在有源半导体膜的未处理区域中形成的互补金属氧化物半导体场效应（CMOSFET）薄膜晶体管（TFT）结构相比，有源膜的激光退火部分中的TFT的TFT阈值电压标准偏差为 n沟道减少60％，p沟道TFT减少30％。
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公开(公告)号：US20090250700A1
公开(公告)日：2009-10-08
申请号：US12099756
申请日：2008-04-08
IPC分类号： H01L29/786 , H01L21/336 , H01L29/76
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02686 , H01L27/1285 , H01L29/66757 , H01L29/66772 , H01L29/785
摘要： A transistor with crystalline semiconductor stripes and an associated fabrication process are provided. The method provides a substrate, and deposits a semiconductor layer overlying the substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, a transistor active semiconductor region is formed including a plurality of crystalline semiconductor stripes oriented along parallel axes. In one aspect, a channel region is formed from the plurality of oriented crystalline semiconductor stripes, and the method forms a gate dielectric overlying the channel region, with a gate electrode overlying the gate dielectric. In another aspect, forming the transistor active semiconductor region includes forming source, drain, and channel regions from the plurality of oriented crystalline semiconductor stripes.
摘要翻译： 提供具有晶体半导体条纹和相关制造工艺的晶体管。 该方法提供衬底，并且沉积覆盖衬底的半导体层。 使用扫描分步重复激光退火工艺照射半导体层，其使半导体层的部分凝聚。 响应于冷却聚集的半导体材料，形成包括沿着平行轴定向的多个晶体半导体条纹的晶体管有源半导体区域。 在一个方面，由多个取向结晶半导体条形成沟道区，该方法形成覆盖沟道区的栅极电介质，栅电极覆盖栅电介质。 在另一方面，形成晶体管有源半导体区域包括从多个取向晶体半导体条形成源极，漏极和沟道区域。
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公开(公告)号：US20090250791A1
公开(公告)日：2009-10-08
申请号：US12099744
申请日：2008-04-08
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02609 , H01L21/02686 , H01L29/78696
摘要： Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, oriented crystalline semiconductor stripes are formed on the insulator substrate. The crystalline semiconductor stripes are aligned approximately with a straight line stripe axis overlying a top surface of the insulating substrate. Each crystalline semiconductor stripe includes a plurality of consecutive ring segments aligned with the stripe axis. The rings segments have a width about equal to the laser annealing process step distance. The crystalline semiconductor stripes typically have a top surface shape of a truncated cylinder or a parabolic cross section.
摘要翻译： 提供了晶体半导体条纹和相关联的制造工艺。 该方法提供绝缘体衬底，并且沉积覆盖绝缘体衬底的半导体层。 使用扫描分步重复激光退火工艺照射半导体层，其使半导体层的部分凝聚。 响应于冷却聚集的半导体材料，在绝缘体基板上形成取向的结晶半导体条纹。 晶体半导体条纹大约与覆盖在绝缘基板的顶表面上的直线条纹轴对准。 每个晶体半导体条纹包括与条纹轴对准的多个连续的环段。 环段具有大约等于激光退火工艺步距的宽度。 晶体半导体条纹通常具有截顶圆柱体的顶表面形状或抛物线截面。
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公开(公告)号：US20090078940A1
公开(公告)日：2009-03-26
申请号：US11904133
申请日：2007-09-26
CPC分类号： H01L29/78672 , H01L27/1277 , H01L27/1285 , H01L29/6675 , H01L29/66757 , H01L29/78603 , H01L29/78648 , H01L29/78675
摘要： A structure with location-controlled crystallization of an active semiconductor film using a crystal seed has been provided, along with an associated fabrication method. The method forms a first semiconductor film overlying a substrate having a crystallographic orientation. Typically, the structure is polycrystalline or single-crystal. The first semiconductor film is selectively etched, forming a seed region. An insulator is formed with an opening, exposing the seed region. An amorphous second semiconductor film is formed over the insulator layer. The second semiconductor film is laser annealed, partially melting the seed region. Crystal grains are laterally grown in the second semiconductor film having the same crystallographic orientation as the seed region. In TFT fabrication an etching is typically performed to remove the second semiconductor film overlying the seed region, and a transistor active region is formed in the remaining second semiconductor film.
摘要翻译： 已经提供了使用晶种的有源半导体膜的位置控制结晶的结构，以及相关的制造方法。 该方法形成了覆盖具有晶体取向的衬底的第一半导体膜。 通常，该结构是多晶或单晶。 选择性地蚀刻第一半导体膜，形成种子区域。 绝缘体形成有开口，暴露种子区域。 在绝缘体层上方形成无定形的第二半导体膜。 第二半导体膜被激光退火，部分熔化种子区域。 在具有与种子区域相同的晶体取向的第二半导体膜中横向生长晶粒。 在TFT制造中，通常进行蚀刻以去除覆盖种子区域的第二半导体膜，并且在剩余的第二半导体膜中形成晶体管有源区。
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5.发明授权公开(公告)号：US08691672B2
公开(公告)日：2014-04-08
申请号：US13433072
申请日：2012-03-28
IPC分类号： B82Y30/00
CPC分类号： H01L29/78651 , B82Y10/00 , H01L29/66757 , H01L29/78603
摘要： A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing.
摘要翻译： 提供一种消耗硅（Si）纳米颗粒膜中的氧化物的方法。 该方法形成了覆盖衬底的Si纳米颗粒的胶体溶液膜。 在钛（Ti）存在下，在高温下对Si纳米颗粒胶体溶液膜进行退火。 响应于退火，在所得Si纳米颗粒膜中消耗Si氧化物。 在一个方面，消耗Si纳米颗粒膜中的Si氧化物包括在Si纳米颗粒膜中形成Ti氧化物。 另外响应于低温退火，溶剂在Si纳米颗粒的胶体溶液膜中蒸发。 响应于高温退火，Si和Ti氧化物分子在Si纳米颗粒膜中烧结。
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公开(公告)号：US07532187B2
公开(公告)日：2009-05-12
申请号：US11184699
申请日：2005-07-18
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.
摘要翻译： 提供了双栅极薄膜晶体管（DG-TFT）电压存储电路。 电路包括电压存储元件，具有连接到数据线的第一源极/漏极（S / D）的DG-TFT，连接到第一栅极线的顶栅极，连接到电压存储器的第二S / D区域 元件和连接到偏置线的底栅。 在一个方面，电路还包括具有连接到第一栅极线的输入的电压移位器和用于在偏置线上提供偏置电压的输出。 电压存储元件的实例包括电容器，液晶（LC）像素和发光二极管（LED）像素。
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公开(公告)号：US20060166415A1
公开(公告)日：2006-07-27
申请号：US11387626
申请日：2006-03-23
CPC分类号： H01L27/1274 , H01L27/1214 , H01L29/78648 , H01L29/78672
摘要： A two-transistor tri-state inverter is provided, made from a NMOS dual-gate thin-film transistor (DG-TFT) having a top gate, a back gate, and source/drain regions. A PMOS DG-TFT also has a top gate, a back gate, and S/D regions, and the NMOS first S/D region is connected to a PMOS first S/D region. The NMOS top gate is connected to an input signal (Vin), the back gate is connected to a control signal (Vb), the first S/D region supplies an output signal (Vout), and a second S/D region is connected to a reference voltage. The PMOS top gate is connected to the input signal, the back gate is connected to an inverted control signal (−Vb), and a second S/D region is connected to a supply voltage having a higher voltage than the reference voltage.
摘要翻译： 提供了由具有顶栅极，后栅极和源极/漏极区域的NMOS双栅极薄膜晶体管（DG-TFT）制成的双晶体管三态反相器。 PMOS DG-TFT还具有顶栅极，背栅极和S / D区域，并且NMOS第一S / D区域连接到PMOS第一S / D区域。 NMOS顶栅连接到输入信号（Vin），背栅极连接到控制信号（Vb），第一S / D区域提供输出信号（Vout），并且第二S / D区域被连接 到参考电压。 PMOS顶栅连接到输入信号，后栅连接到反相控制信号（-Vb），第二S / D区连接到具有比参考电压高的电压的电源电压。
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公开(公告)号：US20140173657A1
公开(公告)日：2014-06-19
申请号：US13713956
申请日：2012-12-13
IPC分类号： H04N21/81
CPC分类号： H04N21/8173 , H04N21/4126 , H04N21/4316
摘要： An Auxiliary Electronic Program Guide (AEPG) television system is provided with a receiver having a network interface to accept broadcast channel information, including programs with visual content and Electronic Program Guide (EPG) information describing the programs. The receiver converts selected programs into display data supplied at a display interface. A display has an input to accept the display data and a screen to present images for the selected channels. An auxiliary module converts the EPG information into a code signal representing the EPG information. A user interface (e.g., the display screen) supplies the code signal to a remote device. For example, the auxiliary module converts the EPG information into code signal enabled as a compact code image, and the display screen presents the compact code as an image. In one aspect, the compact code image is a 2D barcode.
摘要翻译： 辅助电子节目指南（AEPG）电视系统具有接收机，该接收机具有接收广播频道信息的网络接口，包括具有视觉内容的节目和描述节目的电子节目指南（EPG）信息。 接收器将选择的程序转换为显示界面提供的显示数据。 显示器具有接受显示数据的输入和用于呈现所选频道的图像的屏幕。 辅助模块将EPG信息转换为表示EPG信息的代码信号。 用户界面（例如，显示屏幕）将代码信号提供给远程设备。 例如，辅助模块将EPG信息转换为能够作为紧凑代码图像的代码信号，并且显示屏幕将紧凑代码呈现为图像。 在一个方面，紧凑代码图像是2D条形码。
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公开(公告)号：US20130256675A1
公开(公告)日：2013-10-03
申请号：US13433072
申请日：2012-03-28
IPC分类号： H01L29/786 , H01L21/336 , H01L21/20
CPC分类号： H01L29/78651 , B82Y10/00 , H01L29/66757 , H01L29/78603
摘要： A method is provided for consuming oxides in a silicon (Si) nanoparticle film. The method forms a colloidal solution film of Si nanoparticles overlying a substrate. The Si nanoparticle colloidal solution film is annealed at a high temperature in the presence of titanium (Ti). In response to the annealing, Si oxide is consumed in a resultant Si nanoparticle film. In one aspect, the consuming the Si oxide in the Si nanoparticle film includes forming Ti oxide in the Si nanoparticle film. Also in response to a low temperature annealing, solvents are evaporated in the colloidal solution film of Si nanoparticles. Si and Ti oxide molecules are sintered in the Si nanoparticle film in response to the high temperature annealing.
摘要翻译： 提供一种消耗硅（Si）纳米颗粒膜中的氧化物的方法。 该方法形成了覆盖衬底的Si纳米颗粒的胶体溶液膜。 在钛（Ti）存在下，在高温下对Si纳米颗粒胶体溶液膜进行退火。 响应于退火，在所得Si纳米颗粒膜中消耗Si氧化物。 在一个方面，消耗Si纳米颗粒膜中的Si氧化物包括在Si纳米颗粒膜中形成Ti氧化物。 另外响应于低温退火，溶剂在Si纳米颗粒的胶体溶液膜中蒸发。 响应于高温退火，Si和Ti氧化物分子在Si纳米颗粒膜中烧结。
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公开(公告)号：US08236631B2
公开(公告)日：2012-08-07
申请号：US12644061
申请日：2009-12-22
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译： 提供了一个四晶体管施密特触发器。 施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极， 背栅极和源极/漏极区域。 （常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。 （传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。
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