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12 条记录 (耗时 0.014 秒)

    Cryptographic device and methods for defeating physical analysis
    1.
    发明授权
    Cryptographic device and methods for defeating physical analysis 有权
    加密设备和打败物理分析的方法

    公开(公告)号：US07500112B1

    公开(公告)日：2009-03-03

    申请号：US09749142

    申请日：2000-12-27

    申请人： Thomas Wille ,  Wolfgang Hass

    发明人： Thomas Wille ,  Wolfgang Hass

    IPC分类号： G06F21/00

    CPC分类号： G07F7/1008 ,  G06F21/72 ,  G06F21/75 ,  G06F21/755 ,  G06F21/77 ,  G06F2207/7219 ,  G06Q20/341 ,  G07F7/082 ,  H04L9/003 ,  H04L9/0625 ,  H04L2209/08 ,  H04L2209/125

    摘要： The present invention relates to a data-processing device, particularly a chip card or smart card, and to a method of operating said device, with an integrated circuit comprising a central processing unit (CPU) (10) and one or more co-processors (12). The integrated circuit comprises a control unit (18, 30) which controls the processors, CPU (10) and co-processors (12) in such a way that, in the case of a cryptographic operation, at least two processors perform a cryptographic operation simultaneously and in parallel.

    摘要翻译： 本发明涉及一种数据处理设备，特别是芯片卡或智能卡，以及一种操作所述设备的方法，集成电路包括中央处理单元（CPU）（10）和一个或多个协处理器 （12）。 集成电路包括控制单元（18,30），其以这样的方式控制处理器CPU（10）和协处理器（12），使得在密码操作的情况下，至少两个处理器执行密码操作 同时并行。

    Data processing device including a microprocessor and an additional arithmetic unit
    2.
    发明授权
    Data processing device including a microprocessor and an additional arithmetic unit 失效
    数据处理装置包括微处理器和附加运算单元

    公开(公告)号：US5889622A

    公开(公告)日：1999-03-30

    申请号：US903566

    申请日：1997-07-31

    申请人： Thomas Wille ,  Ralf Malzahn ,  Jean-Jaques Quisquater ,  Ronald Ferreira

    发明人： Thomas Wille ,  Ralf Malzahn ,  Jean-Jaques Quisquater ,  Ronald Ferreira

    IPC分类号： G06F15/16 ,  G06F9/318 ,  G06F9/38 ,  H04K1/00 ,  G06F7/38

    CPC分类号： G06F9/30156 ,  G06F9/30138 ,  G06F9/3885

    摘要： The arithmetic unit in a data processing system with a microprocessor and an additional arithmetic unit carries out special arithmetic operations, preferably integrated in a single semiconductor chip, is controlled by the microprocessor via a number of registers. Several sets of such registers are provided. The registers of one set are selected via a selection circuit. As a result, a set of registers which is not required during execution of a calculation by the arithmetic unit can be filled with new data by the microprocessor and, after completion of the calculation in the arithmetic unit, switching over to a newly filled set of registers takes place so that the arithmetic unit can continue with a new set of operands without having to observe a waiting period.

    摘要翻译： 具有微处理器和附加运算单元的数据处理系统中的算术单元执行优选地集成在单个半导体芯片中的特殊算术运算由微处理器经由多个寄存器来控制。 提供了几组这样的寄存器。 通过选择电路选择一组寄存器。 结果，可以通过微处理器填充由运算单元执行计算而不需要的一组寄存器，并且在算术单元中的计算完成之后切换到新填充的一组 发生寄存器，使得算术单元可以继续新的一组操作数而不必观察等待期。

    DATA CARRIER WITH A CHIP AND A PLURALITY OF SENSORS
    3.
    发明申请
    DATA CARRIER WITH A CHIP AND A PLURALITY OF SENSORS 有权
    数据载体与芯片和传感器的多样性

    公开(公告)号：US20090294535A1

    公开(公告)日：2009-12-03

    申请号：US11721433

    申请日：2005-12-06

    申请人： Manfred Paeschke ,  Kim Nguyen ,  Oliver Muth ,  Michael Knebel ,  Matthias Wagner ,  Thomas Wille

    发明人： Manfred Paeschke ,  Kim Nguyen ,  Oliver Muth ,  Michael Knebel ,  Matthias Wagner ,  Thomas Wille

    IPC分类号： G06K7/00 ,  G06K19/06

    CPC分类号： G06K19/07749 ,  G06K7/1097 ,  G06K19/0716 ,  G06K19/0723 ,  G06K19/0728 ,  G06K19/073 ,  G06K19/07345 ,  G06K19/077 ,  G06K19/145 ,  H01L31/02162 ,  H01L31/02322

    摘要： The invention relates to a data carrier (100) with a chip (10) which stores energy (13) as well as information for contact-bound or contactless inductive communication, and with a plurality of excitable chip sensors (11) integrated in the chip (10), which, after excitation (12), pass on a signal (18) to a CPU (19) of the chip (10), in which the signal (18) is processed. The invention is characterized in that, independently of storing energy (13) as well as information by the chip (10), the excitation (12) is specifically adjustable by the chip (10) for the purpose of additionally storing information and is adaptable to the requirements of processing the signal (18) in the CPU (19).

    摘要翻译： 本发明涉及一种具有芯片（10）的数据载体（100），其存储能量（13）以及用于接触界限或非接触感应通信的信息，以及集成在芯片中的多个可激励的芯片传感器（11） （10），其在激励（12）之后将信号（18）传递到其中对信号（18）进行处理的芯片（10）的CPU（19）。 本发明的特征在于，独立于存储能量（13）以及芯片（10）的信息，激励（12）可以由芯片（10）特别地调整，以便另外存储信息，并且适用于 处理CPU（19）中的信号（18）的要求。

    Forgery prevention microcontroller circuit
    4.
    发明授权
    Forgery prevention microcontroller circuit 有权
    防伪微控制器电路

    公开(公告)号：US06334206B1

    公开(公告)日：2001-12-25

    申请号：US09265778

    申请日：1999-03-10

    申请人： Thomas Wille

    发明人： Thomas Wille

    IPC分类号： G06F1570

    CPC分类号： H01L27/0203 ,  G06F12/1425 ,  G06F21/75 ,  G06F2207/7219

    摘要： The invention relates to a microcontroller circuit, comprising circuit elements arranged on a semiconductor body. In order to make a tentative forgery of such a microcontroller circuit at least more difficult, at least a number of the co-operating circuit elements is provided on the semiconductor body in an irregularly scrambled spatial configuration.

    摘要翻译： 本发明涉及一种微控制器电路，其包括设置在半导体本体上的电路元件。 为了使这种微控制器电路的暂时伪造至少更加困难，至少多个协作电路元件以不规则加扰的空间配置提供在半导体主体上。

    Tag communication devices
    5.
    发明授权
    Tag communication devices 有权
    标记通信设备

    公开(公告)号：US08441340B2

    公开(公告)日：2013-05-14

    申请号：US13047400

    申请日：2011-03-14

    申请人： Franz Amtmann ,  Thomas Wille ,  Hauke Meyn ,  Mathias Wagner

    发明人： Franz Amtmann ,  Thomas Wille ,  Hauke Meyn ,  Mathias Wagner

    IPC分类号： H04Q5/22

    CPC分类号： G06K7/0008

    摘要： A contactless tag reader device comprises upper and lower electrodes which together define a tag location zone between them in which multiple tags can be placed. The lower electrode and the upper electrode are offset from each other such that they substantially do not overlap. This structure is used to sandwich tags vertically between two horizontally (laterally) offset reader electrodes. This enables power coupling and data transfer using capacitive coupling.

    摘要翻译： 非接触式标签读取器装置包括上部和下部电极，它们一起在它们之间限定可放置多个标签的标签位置区域。 下电极和上电极彼此偏移，使得它们基本上不重叠。 这种结构用于在两个水平（横向）偏移读取器电极之间垂直夹置标签。 这使得能够使用电容耦合进行功率耦合和数据传输。

    Circuit arrangement for generating a binary output signal
    6.
    发明授权
    Circuit arrangement for generating a binary output signal 失效
    用于产生二进制输出信号的电路装置

    公开(公告)号：US5834959A

    公开(公告)日：1998-11-10

    申请号：US709503

    申请日：1996-09-06

    申请人： Siegfried Ritter ,  Thomas Wille ,  Rolf Tammer

    发明人： Siegfried Ritter ,  Thomas Wille ,  Rolf Tammer

    IPC分类号： H04L25/40 ,  G06K7/00 ,  H03K5/1252 ,  H04L7/02 ,  H03K5/151

    CPC分类号： H03K5/1252 ,  G06K7/0008

    摘要： In order to generate a non-disturbed binary output signal from a disturbed input signal, notably if the latter is periodic in the non-disturbed state, the invention proposes a circuit arrangement which includes two circuit branches which respond to different edge directions of the input signal. Each branch includes two series-connected flipflops and there is also provided a timing member which is common to the two circuit branches. As a result of a coupling of the two circuit branches to one another it is achieved that, after the triggering of one circuit branch, the other branch is blocked. Triggering of the other circuit branch is possible only after the delay time of the timing member has elapsed. It is thus achieved that the edges of the binary output signal have a minimum temporal spacing or that the binary output signal does not exceed a maximum frequency. Furthermore, a transition of the input signal is evaluated also if it occurs prior to the elapsing of the delay time. Evaluation of the signals in both circuit branches enables formation of two non-overlapping output signals.

    摘要翻译： 为了从干扰的输入信号产生未干扰的二进制输出信号，特别是如果后者在非干扰状态下是周期性的，本发明提出一种电路装置，其包括响应输入的不同边缘方向的两个电路分支 信号。 每个分支包括两个串联连接的触发器，并且还提供了两个电路分支通用的定时部件。 作为两个电路分支彼此耦合的结果，实现了在一个电路分支的触发之后，另一个分支被阻止。 只有在定时构件的延迟时间过去之后才可能触发另一个电路支路。 因此实现二进制输出信号的边缘具有最小时间间隔或二进制输出信号不超过最大频率。 此外，如果在延迟时间过去之前发生输入信号的转换，则也进行评估。 对两个电路分支中的信号进行评估可以形成两个不重叠的输出信号。

    Polymer prosthesis
    7.
    发明授权
    Polymer prosthesis 有权
    聚合物假体

    公开(公告)号：US08672995B2

    公开(公告)日：2014-03-18

    申请号：US12064233

    申请日：2006-08-21

    申请人： Thiemo Blank ,  Thomas Wille

    发明人： Thiemo Blank ,  Thomas Wille

    IPC分类号： A61F2/82

    CPC分类号： A61F2/89 ,  A61F2002/072 ,  A61F2002/825 ,  A61F2002/828 ,  A61F2220/005 ,  A61F2220/0058 ,  A61F2250/0018

    摘要： A polymer prosthesis with lumen and an axial length and having in a pre-delivery condition a plurality of relatively stiff stenting segments spaced from each other along the length of the prosthesis, the spaces between the relatively stiff stenting segments of a first polymer being bridged by relatively flexible linking segments of a second polymer, different from the first, the relatively stiff stenting segments and the relatively flexible linking segments being alternately arranged along the length of the prosthesis.

    摘要翻译： 一种具有内腔和轴向长度的聚合物假体，并且在预交付状态下具有沿假体长度彼此间隔开的多个相对较硬的支架构件段，第一聚合物的较硬的支架段之间的空间由 不同于第一聚合物的相对柔性的连接段，相对较硬的支架段和相对柔性的连接段沿假体的长度交替排列。

    POLYMER PROSTHESIS
    10.
    发明申请
    POLYMER PROSTHESIS 有权
    聚合物预处理

    公开(公告)号：US20100319836A1

    公开(公告)日：2010-12-23

    申请号：US12064233

    申请日：2006-08-21

    申请人： Thiemo Blank ,  Thomas Wille

    发明人： Thiemo Blank ,  Thomas Wille

    IPC分类号： B29D23/00 ,  A61F2/82

    CPC分类号： A61F2/89 ,  A61F2002/072 ,  A61F2002/825 ,  A61F2002/828 ,  A61F2220/005 ,  A61F2220/0058 ,  A61F2250/0018

    摘要： A polymer prosthesis with lumen and an axial length and having in a pre-delivery condition a plurality of relatively stiff stenting segments spaced from each other along the length of the prosthesis, the spaces between the relatively stiff stenting segments of a first polymer being bridged by relatively flexible linking segments of a second polymer, different from the first, the relatively stiff stenting segments and the relatively flexible linking segments being alternately arranged along the length of the prosthesis.

    摘要翻译： 一种具有内腔和轴向长度的聚合物假体，并且在预交付状态下具有沿假体长度彼此间隔开的多个相对较硬的支架构件段，第一聚合物的较硬的支架段之间的空间由 不同于第一聚合物的相对柔性的连接段，相对较硬的支架段和相对柔性的连接段沿假体的长度交替排列。