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17 条记录 (耗时 0.037 秒)

    Reliability of wide interconnects
    2.
    发明授权
    Reliability of wide interconnects 失效
    宽互连的可靠性

    公开(公告)号：US07776737B2

    公开(公告)日：2010-08-17

    申请号：US12191534

    申请日：2008-08-14

    申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

    发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

    IPC分类号： H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76816 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.

    摘要翻译： 一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别 包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线 在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。 还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。

    RELIABILITY OF WIDE INTERCONNECTS
    3.
    发明申请
    RELIABILITY OF WIDE INTERCONNECTS 失效
    宽互联的可靠性

    公开(公告)号：US20100038790A1

    公开(公告)日：2010-02-18

    申请号：US12191534

    申请日：2008-08-14

    申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

    发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus Eduardus Standaert

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76816 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.

    摘要翻译： 一种集成电路，其包括半导体衬底，所述半导体衬底上的包括金属布线的第一金属布线级别，所述第一金属布线层上的互连布线级别，其包括层间电介质内的通孔布线，第二金属布线级别 包括金属布线的互连布线层，至少一个具有多个介电填充形状的金属布线，其减小了所述至少一个金属布线的横截面积，并且其中所述通孔互连使金属线 在第一布线级别和第二布线级中的至少一个金属布线中，通孔布线与多个介质填充形状相邻并间隔开。 还公开了一种方法，其中多个介电填充形状被放置成与第二布线层中的布线中的通孔接触区域相邻并间隔开。

    Damascene interconnection having a SiCOH low k layer
    6.
    发明申请
    Damascene interconnection having a SiCOH low k layer 审中-公开
    具有SiCOH低k层的镶嵌互连

    公开(公告)号：US20070232048A1

    公开(公告)日：2007-10-04

    申请号：US11395962

    申请日：2006-03-31

    申请人： Koji Miyata ,  Sujatha Sankaran ,  Theodorus Eduardus Standaert ,  Ricardo Donaton

    发明人： Koji Miyata ,  Sujatha Sankaran ,  Theodorus Eduardus Standaert ,  Ricardo Donaton

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76811 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76813

    摘要： A method and apparatus is provided for fabricating a damascene interconnection. The method begins by forming on a substrate an organosilicate dielectric layer, a capping layer on the organosilicate dielectric layer, and a resist pattern over the capping layer to define a first interconnect opening. The capping layer is etched through the resist pattern using a first etchant. The resist pattern is removed after etching the capping layer. The dielectric layer is etched through the capping layer using a second etchant different from the first etchant to form the first interconnect opening. An interconnection is completed by filling the first interconnect opening with conductive material.

    摘要翻译： 提供了一种用于制造镶嵌互连的方法和装置。 该方法开始于在基底上形成有机硅酸盐介电层，有机硅酸盐介电层上的覆盖层，以及覆盖层上的抗蚀剂图案，以限定第一互连开口。 使用第一蚀刻剂将覆盖层蚀刻通过抗蚀剂图案。 在蚀刻覆盖层之后去除抗蚀剂图案。 使用不同于第一蚀刻剂的第二蚀刻剂，通过覆盖层蚀刻电介质层以形成第一互连开口。 通过用导电材料填充第一互连开口来完成互连。