公开(公告)号：US20070284575A1

公开(公告)日：2007-12-13

申请号：US11893402

申请日：2007-08-15

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

IPC分类号： H01L29/12

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

摘要翻译： 提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。 可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

公开(公告)号：US20070108502A1

公开(公告)日：2007-05-17

申请号：US11281955

申请日：2005-11-17

申请人： Tingkai Li ,  Sheng Hsu ,  Lisa Stecker

发明人： Tingkai Li ,  Sheng Hsu ,  Lisa Stecker

IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C16/04

CPC分类号： H01L29/7881 ,  B82Y10/00 ,  G11C16/349 ,  G11C16/3495 ,  G11C2216/08 ,  H01L29/15 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4925 ,  H01L29/66825

摘要： A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).

摘要翻译： 已经提供了纳米晶体硅（Si）量子点存储器件和相关的制造方法。 该方法包括：形成覆盖Si衬底有源层的栅极（隧道）氧化层; 形成覆盖栅极氧化物层的纳米晶Si记忆膜，包括多晶Si（多晶硅）/二氧化硅叠层; 形成覆盖在纳米晶Si记忆膜上的对照Si氧化物层; 形成覆盖所述控制氧化物层的栅电极; 并且在Si有源层中形成源/漏区。 在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层（a-Si）并热氧化a-Si层的一部分来形成纳米晶体Si记忆膜。 通常，重复a-Si沉积和氧化过程，形成多个多Si /二氧化硅叠层（即2至5个多硅/二氧化硅叠层）。

公开(公告)号：US20070015330A1

公开(公告)日：2007-01-18

申请号：US11435669

申请日：2006-05-17

申请人： Tingkai Li ,  Sheng Hsu ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  David Evans

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

公开(公告)号：US20070015328A1

公开(公告)日：2007-01-18

申请号：US11184660

申请日：2005-07-18

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

公开(公告)号：US20060194403A1

公开(公告)日：2006-08-31

申请号：US11378719

申请日：2006-03-17

申请人： Tingkai Li ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/20

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1

摘要翻译： 已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。 在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜 组成，其中0.1 _0.78Mn^{4+<​​/SUP>_0.22O2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。 在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。 例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

公开(公告)号：US20060172555A1

公开(公告)日：2006-08-03

申请号：US11049594

申请日：2005-02-01

申请人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/31

CPC分类号： C23C14/5806 ,  C23C14/10

摘要： A method of forming a silicon-rich silicon oxide layer having nanometer sized silicon particles therein includes preparing a substrate; preparing a target; placing the substrate and the target in a sputtering chamber; setting the sputtering chamber parameters; depositing material from the target onto the substrate to form a silicon-rich silicon oxide layer; and annealing the substrate to form nanometer sized silicon particles therein.

摘要翻译： 形成其中具有纳米尺寸硅颗粒的富硅氧化硅层的方法包括制备衬底; 准备一个目标 将基板和靶放置在溅射室中; 设置溅射室参数; 将材料从靶材沉积到衬底上以形成富硅氧化硅层; 并对衬底退火以在其中形成纳米尺寸的硅颗粒。

公开(公告)号：US20060068099A1

公开(公告)日：2006-03-30

申请号：US10957304

申请日：2004-09-30

申请人： Tingkai Li ,  Lawrence Charneski ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

发明人： Tingkai Li ,  Lawrence Charneski ,  Wei-Wei Zhuang ,  David Evans ,  Sheng Hsu

IPC分类号： C23C16/00

CPC分类号： C23C16/40 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： The present invention discloses a method to achieve grading PCMO thin film for use in RRAM memory devices since the contents of Ca, Mn and Pr in a PCMO film can have great influence on its switching property. By choosing precursors for Pr, Ca and Mn having different deposition rate behaviors with respect to deposition temperature or vaporizer temperature, PCMO thin film of grading Pr, Ca or Mn distribution can be achieved by varying that process condition during deposition. The present invention can also be broadly applied to the fabrication of any multicomponent grading thin film process by varying any of the deposition parameters after preparing multiple precursors to have different deposition rate behaviors with respect to that particular process parameter. The present invention starts with a proper selection of precursors in which the selected precursors have different deposition rates with respect to at least one deposition condition such as deposition temperature or vaporizer temperature. The precursors can then be arranged in different delivery systems, or can be pre-mixed in a proper ratio for use in a delivery system, or in any other combinations such as a mixture of two or three liquid precursors using a direct liquid injection and a separate gaseous precursor delivery system for gaseous process gas. Then by varying the appropriate deposition condition, a grading thin film can be achieved.

摘要翻译： 本发明公开了一种用于RRAM存储器件中的PCMO薄膜分级的方法，因为PCMO薄膜中Ca，Mn和Pr的含量对其开关性能有很大的影响。 通过选择相对于沉积温度或蒸发器温度具有不同沉积速率行为的Pr，Ca和Mn的前体，可以通过在沉积期间改变该工艺条件来实现分级Pr，Ca或Mn分布的PCMO薄膜。 本发明还可以广泛地应用于任何多组分分级薄膜工艺的制造，其通过在制备多种前体之后改变任何沉积参数以相对于该特定工艺参数具有不同的沉积速率行为。 本发明开始于适当选择前体，其中所选择的前体相对于至少一个沉积条件例如沉积温度或蒸发器温度具有不同的沉积速率。 然后可将前体布置在不同的递送系统中，或者可以以适当的比例预先混合以用于递送系统，或者以任何其它组合例如使用直接液体注射的两种或三种液体前体的混合物 用于气态工艺气体的单独的气态前体输送系统。 然后通过改变适当的沉积条件，可以实现分级薄膜。

公开(公告)号：US20050266686A1

公开(公告)日：2005-12-01

申请号：US10855088

申请日：2004-05-27

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David Evans ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David Evans ,  Sheng Hsu

IPC分类号： C23C18/12 ,  C30B23/02 ,  C30B29/24 ,  H01L21/44 ,  H01L45/00

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1241 ,  C23C18/1283 ,  C30B23/02 ,  C30B29/24 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1608

摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

摘要翻译： 制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

公开(公告)号：US20050151210A1

公开(公告)日：2005-07-14

申请号：US10755419

申请日：2004-01-12

申请人： Tingkai Li ,  Sheng Hsu

发明人： Tingkai Li ,  Sheng Hsu

IPC分类号： H01L21/28 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28291 ,  H01L29/78391

摘要： The present invention discloses a novel ferroelectric transistor design using a resistive oxide film in place of the gate dielectric. By replacing the gate dielectric with a resistive oxide film, and by optimizing the value of the film resistance, the bottom gate of the ferroelectric layer is electrically connected to the silicon substrate, eliminating the trapped charge effect and resulting in the improvement of the memory retention characteristics. The resistive oxide film is preferably a doped conductive oxide in which a conductive oxide is doped with an impurity species. The doped conductive oxide is most preferred to be In2O3 with the dopant species being hafnium oxide, zirconium oxide, lanthanum oxide, or aluminum oxide.

摘要翻译： 本发明公开了一种使用电阻氧化膜代替栅极电介质的新型铁电晶体管设计。 通过用电阻氧化膜代替栅极电介质，并且通过优化膜电阻的值，铁电层的底栅电连接到硅衬底，消除了捕获的电荷效应并导致存储保持率的提高 特点 电阻氧化膜优选为其中掺杂有杂质物质的导电氧化物的掺杂导电氧化物。 掺杂的导电氧化物最优选为掺杂物质为氧化铪，氧化锆，氧化镧或氧化铝的In 2 N 3 O 3。

公开(公告)号：US20070272960A1

公开(公告)日：2007-11-29

申请号：US11890692

申请日：2007-08-07

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L29/76

CPC分类号： G11C11/22 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391

摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

摘要翻译： 本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。 导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。 通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。 消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。 还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。