摘要:
Pieces of working information on workloads, positions of the workloads, pieces of environmental information on cooling facilities, and positions of the cooling facilities are stored as arrangement information. The pieces of working information on the workloads are estimated, and allocation of tentative workloads is deduced for fear the pieces of working information may exceed the performances of a group of information processing devices. Tentative power consumptions and arrangement information resulting from the allocation of the tentative workloads, and tentative power consumptions and arrangement information necessary for the allocation of the tentative workloads are calculated. Tentative cooling powers required to control the cooling facilities are calculated. Allocation of the tentative workloads minimizing the sum total of the tentative power consumptions of the information processing devices and the tentative cooling powers of the cooling facilities is searched. Based on the searched allocation, the workloads are allocated to the information processing devices.
摘要:
Pieces of working information on workloads, positions of the workloads, pieces of environmental information on cooling facilities, and positions of the cooling facilities are stored as arrangement information. The pieces of working information on the workloads are estimated, and allocation of tentative workloads is deduced for fear the pieces of working information may exceed the performances of a group of information processing devices. Tentative power consumptions and arrangement information resulting from the allocation of the tentative workloads, and tentative power consumptions and arrangement information necessary for the allocation of the tentative workloads are calculated. Tentative cooling powers required to control the cooling facilities are calculated. Allocation of the tentative workloads minimizing the sum total of the tentative power consumptions of the information processing devices and the tentative cooling powers of the cooling facilities is searched. Based on the searched allocation, the workloads are allocated to the information processing devices.
摘要:
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.
摘要:
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.
摘要:
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.
摘要:
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.
摘要:
As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path. Further, an interposer for facilitating the connection with the processor LSI is connected to the input terminal of the memory LSI to be stacked thereby increasing the degree of freedom in selecting memories.
摘要:
A semiconductor integrated circuit with processors incorporated therein, which makes it possible to achieve a good balance between realizing low-power consumption control, and securing a processing performance that the practicability of real time processing is required.The semiconductor integrated circuit with processors incorporated therein is provided with a management unit, combining first control for changing a value of the voltage and a frequency of the clock signal based on control information contained in the program, and second control for changing the voltage value and clock signal frequency according to a progress status of a process by the processor, thereby to accelerate progress of the process by the processor. In a period during which the frequency and voltage of each processor are raised, the power consumption is increased, however it becomes possible to achieve high-speed processing. While in a period during which neither frequency nor voltage of each processor are raised, high-speed processing cannot be performed, however, the power consumption is small. Thus, it is possible to achieve a good balance between to materialize low-power consumption control in a semiconductor integrated circuit with processors incorporated therein, and to ensure a processing performance that the practicability of real time processing is required.