公开(公告)号：US10008564B2

公开(公告)日：2018-06-26

申请号：US15342968

申请日：2016-11-03

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Ying Trickett ,  Chihiro Tamura ,  Cory Wajda ,  Gerrit J. Leusink ,  Kaoru Maekawa

IPC: H01L21/311 ,  H01L21/30 ,  H01L21/46 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/0673 ,  H01J37/32192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/16 ,  H01L29/775

Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.

公开(公告)号：US20170125517A1

公开(公告)日：2017-05-04

申请号：US15342968

申请日：2016-11-03

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Ying Trickett ,  Chihiro Tamura ,  Cory Wajda ,  Gerrit J. Leusink ,  Kaoru Maekawa

IPC: H01L29/06 ,  H01L21/311 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01J37/32192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/16 ,  H01L29/775

Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.

公开(公告)号：US09418837B2

公开(公告)日：2016-08-16

申请号：US14504915

申请日：2014-10-02

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koji Akiyama ,  Hirokazu Higashijima ,  Chihiro Tamura ,  Shintaro Aoyama ,  Yu Wamura

IPC: H01L21/02 ,  C23C16/56 ,  H01L21/67 ,  C23C16/40 ,  H01L21/28 ,  H01L29/51 ,  C23C16/06 ,  C23C16/46 ,  C23C16/52 ,  H01L29/40 ,  H01L49/02

CPC classification number: H01L21/02356 ,  C23C16/06 ,  C23C16/405 ,  C23C16/46 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28158 ,  H01L21/28185 ,  H01L21/67109 ,  H01L21/67115 ,  H01L28/40 ,  H01L29/401 ,  H01L29/517

Abstract: A semiconductor device manufacturing method that includes: forming a gate insulating film containing a hafnium oxide and a zirconium oxide on a workpiece having a source, a drain and a channel; and subjecting the gate insulating film to a crystallization heat treatment at a temperature of 600 degrees C. or less is provided. The gate insulating film subjected to the crystallization heat treatment has a relative permittivity of 27 or more.

Abstract translation: 一种半导体器件制造方法，包括：在具有源极，漏极和沟道的工件上形成含有氧化铪和氧化锆的栅极绝缘膜; 并且在600℃或更低的温度下对栅极绝缘膜进行结晶热处理。 进行结晶热处理的栅极绝缘膜的相对介电常数为27以上。