公开(公告)号：US10825688B2

公开(公告)日：2020-11-03

申请号：US16308428

申请日：2017-06-07

Applicant: TOKYO ELECTRON LIMITED

Inventor： Shigeru Tahara ,  Daisuke Urayama ,  Kenji Matsumoto ,  Hidenori Miyoshi

IPC: H01L21/3065 ,  C23F4/00 ,  H01L21/3213 ,  H01L23/532 ,  H05H1/46

Abstract: A method MT in an embodiment is a method for etching an etching target layer EL which is included in a wafer W and contains copper. The wafer W includes the etching target layer EL, and a mask MK provided on the etching target layer EL. In the method MT, the etching target layer EL is etched by repeatedly executing a sequence SQ including a first step of generating a plasma of a first gas in a processing container 12 of a plasma processing apparatus 10 in which the wafer W is accommodated, a second step of generating a plasma of a second gas in the processing container 12, and a third step of generating a plasma of a third gas in the processing container 12. The first gas contains a hydrocarbon gas, the second gas contains either a rare gas or a mixed gas of a rare gas and hydrogen gas, and the third gas contains hydrogen gas.

公开(公告)号：US10163699B2

公开(公告)日：2018-12-25

申请号：US15553608

申请日：2016-01-07

Applicant: Tokyo Electron Limited

Inventor： Hiroyuki Nagai ,  Peng Chang ,  Kenji Matsumoto

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  C23C14/34 ,  C23C14/58 ,  C23C16/06 ,  C23C16/56 ,  H01L23/528 ,  C23C14/02 ,  C23C14/04 ,  C23C14/16 ,  C23C16/04 ,  H01L23/532

Abstract: A method of forming, on a substrate having on a surface thereof a film having a trench of a preset pattern and a via at a bottom of the trench, a Cu wiring by burying Cu or Cu alloy in the trench and the via includes forming a barrier film (process 2); forming, on a surface of the barrier film, a wetting target layer of Ru or the like (process 3); forming, on a surface of the wetting target layer, a Cu-based seed film by PVD (process 4); filling the via by heating the substrate and flowing the Cu-based seed film into the via (process 5); and forming, on the substrate surface, a Cu-based film made of the Cu or Cu alloy by PVD under a condition where the Cu-based film is flown on the wetting target layer to bury the Cu-based film in the trench (process 6).

公开(公告)号：US09362166B2

公开(公告)日：2016-06-07

申请号：US14642331

申请日：2015-03-09

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro Ishizaka ,  Takashi Sakuma ,  Osamu Yokoyama ,  Kenji Matsumoto ,  Peng Chang ,  Hiroyuki Nagai

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a copper wiring buried in a recess portion of a predetermined pattern formed in an interlayer insulation layer of a substrate is disclosed. The method includes: forming a manganese oxide film at least on a surface of the recess portion, the manganese oxide film serving as a self-aligned barrier film through reaction with the interlayer insulation layer; performing hydrogen radical treatment with respect to a surface of the manganese oxide film; placing a metal more active than ruthenium on the surface of the manganese oxide film after the hydrogen radical treatment; forming a ruthenium film on the surface where the metal more active than ruthenium is present; and forming a copper film on the ruthenium film by physical vapor deposition (PVD) to bury the copper film in the recess portion.

Abstract translation: 公开了一种埋设在衬底的层间绝缘层中形成的预定图案的凹部中的铜布线的形成方法。 该方法包括：通过与层间绝缘层反应，至少在凹部的表面上形成氧化锰膜，氧化锰膜作为自对准阻挡膜; 相对于氧化锰膜的表面进行氢自由基处理; 在氧自由基处理之后，将比钌更金属的氧化物膜置于氧化锰膜的表面上; 在其上存在比钌更有活性的金属的表面上形成钌膜; 并通过物理气相沉积（PVD）在钌膜上形成铜膜以将铜膜埋入凹部中。

公开(公告)号：US20200035465A1

公开(公告)日：2020-01-30

申请号：US16522979

申请日：2019-07-26

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kenji Matsumoto

IPC: H01J37/32 ,  H01L21/687

Abstract: A substrate processing apparatus includes a substrate mounting unit, a support unit, a thickness variable layer, and a control unit. The substrate mounting unit has an upper surface that serves as a mounting surface on which a target substrate to be processed is mounted. The support unit has therein a flow path for a heat transfer medium and is configured to support the substrate mounting unit. The thickness variable layer is disposed between the substrate mounting unit and the support unit, and a thickness of the thickness variable layer changes due to expansion or shrinkage caused by a predetermined process. The control unit is configured to control the thickness of the thickness variable layer by performing the predetermined process.

公开(公告)号：US09735046B2

公开(公告)日：2017-08-15

申请号：US15250109

申请日：2016-08-29

Applicant: TOKYO ELECTRON LIMITED

Inventor： Peng Chang ,  Kenji Matsumoto ,  Hiroyuki Nagai

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76814 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/76823 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238

Abstract: A method of manufacturing a semiconductor device includes preparing a substrate having an interlayer insulating film and a hard mask provided on the interlayer insulating film and having a predetermined pattern, etching the interlayer insulating film to form a trench, forming a MnOx film through an ALD method in a state where the hard mask is left on the interlayer insulating film, the MnOx film being turned into a self-forming barrier film by reacting with the interlayer insulating film, performing a hydrogen radical processing on the MnOx film, forming a Ru film through a CVD method, forming a Cu-based film through a PVD method or by forming a Cu seed through the PVD method, and then performing a Cu plating processing so as to embed the Cu-based film within the trench, and performing a CMP method to remove the hard mask and to form a Cu wiring.

公开(公告)号：US09245847B2

公开(公告)日：2016-01-26

申请号：US14510388

申请日：2014-10-09

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kenji Matsumoto ,  Tatsufumi Hamada ,  Kaoru Maekawa

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  C23C16/06 ,  C23C16/40 ,  C23C16/455 ,  C23C16/46 ,  C23C16/50 ,  H01L21/67 ,  C23C16/04 ,  C23C16/56

CPC classification number: H01L23/53238 ,  C23C16/045 ,  C23C16/06 ,  C23C16/40 ,  C23C16/401 ,  C23C16/45525 ,  C23C16/45544 ,  C23C16/46 ,  C23C16/50 ,  C23C16/56 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/67207 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76864 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device for forming a metal element-containing layer on an insulating layer in which a concave portion is formed, includes: forming an oxide layer including mainly an oxide of the metal element on the insulating layer including the concave portion; and forming a silicate layer including mainly a silicate of the metal element by making the oxide layer into silicate by annealing under a reducing atmosphere.

Abstract translation: 一种在形成有凹部的绝缘层上形成含金属元素层的半导体装置的制造方法，其特征在于，包括：在包括所述凹部的绝缘层上形成主要包含所述金属元素的氧化物的氧化物层; 通过在还原气氛下进行退火，使氧化物层成为硅酸盐，形成主要由金属元素的硅酸盐构成的硅酸盐层。

公开(公告)号：US09153481B2

公开(公告)日：2015-10-06

申请号：US14139089

申请日：2013-12-23

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kenji Matsumoto

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76882 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manganese-containing film forming method for forming a manganese-containing film on an underlying layer containing silicon and oxygen includes: degassing the underlying layer formed on a processing target by thermally treating the processing target, the underlying layer containing silicon and oxygen; and forming a manganese metal film on the degassed underlying layer by chemical deposition using a gas containing a manganese compound. Forming a manganese metal film includes: setting a film formation temperature to be higher than a degassing temperature; introducing a reducing reaction gas; and forming a manganese-containing film including an interfacial layer formed in an interface with the underlying layer and a manganese metal film formed on the interfacial layer, the interfacial layer being made up of a film of at least one of a manganese silicate and a manganese oxide.

Abstract translation: 在含有硅和氧的下层上形成含锰膜的含锰膜形成方法包括：通过热处理处理目标，含有硅和氧的下层，对形成在处理目标上的下层进行脱气; 以及通过使用含有锰化合物的气体进行化学沉积在脱气的下层上形成锰金属膜。 形成锰金属膜包括：将成膜温度设定为高于脱气温度; 引入还原反应气体; 以及形成包含与下层形成界面的界面层和在界面层上形成的锰金属膜的含锰膜，所述界面层由硅酸锰和锰中的至少一种的膜构成 氧化物。

公开(公告)号：US20140361436A1

公开(公告)日：2014-12-11

申请号：US14464875

申请日：2014-08-21

Applicant: Tokyo Electron Limited

Inventor： Kenji Matsumoto ,  Tatsufumi Hamada

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76883 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device manufacturing method includes forming a second conductive layer on an underlying layer which has an insulating layer in which a recess is formed and a first conductive layer exposed on a bottom surface of the recess; forming a third conductive layer on the second conductive layer; supplying, into the third conductive layer, a material solid-soluble in the third conductive layer; and heating the third conductive layer into which the solid-soluble material is supplied.

Abstract translation: 半导体器件制造方法包括在下层上形成第二导电层，所述第二导电层具有其中形成凹部的绝缘层和暴露在所述凹部的底表面上的第一导电层; 在所述第二导电层上形成第三导电层; 向所述第三导电层提供固溶于所述第三导电层中的材料; 并加热其中供应固体可溶性材​​料的第三导电层。

公开(公告)号：US10096548B2

公开(公告)日：2018-10-09

申请号：US15072165

申请日：2016-03-16

Applicant: Tokyo Electron Limited

Inventor： Kenji Matsumoto ,  Tadahiro Ishizaka ,  Peng Chang ,  Osamu Yokoyama ,  Takashi Sakuma ,  Hiroyuki Nagai

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

Abstract: In a Cu wiring manufacturing method, a MnOx film which becomes a self-formed barrier film by reaction with an interlayer insulating film of a substrate is formed on a surface of a recess formed in the interlayer insulating film by ALD. A hydrogen radical process is performed on a surface of the MnOx film to reduce the surface of the MnOx film. A Ru film is formed by CVD on the surface of the MnOx film which has been reduced by the hydrogen radical process. A Cu-based film is formed on the Ru film by PVD to be filled in the recess. When the Ru film is formed, a film-formation condition of the MnOx film and a condition of the hydrogen radical process are set such that nucleus formation is facilitated and the Ru film is formed in a state where a surface smoothness is high.

公开(公告)号：US20180047624A1

公开(公告)日：2018-02-15

申请号：US15553608

申请日：2016-01-07

Applicant: Tokyo Electron Limited

Inventor： Hiroyuki Nagai ,  Peng Chang ,  Kenji Matsumoto

IPC: H01L21/768 ,  C23C16/56 ,  C23C16/46 ,  H01L23/528 ,  C23C14/14 ,  C23C14/58 ,  H01L21/285 ,  H01L23/532 ,  C23C16/06 ,  C23C14/34

CPC classification number: H01L21/76882 ,  C23C14/025 ,  C23C14/046 ,  C23C14/165 ,  C23C14/34 ,  C23C14/5806 ,  C23C16/045 ,  C23C16/06 ,  C23C16/56 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/76843 ,  H01L21/76853 ,  H01L21/76876 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/532 ,  H01L23/53228 ,  H01L23/53238

Abstract: A method of forming, on a substrate having on a surface thereof a film having a trench of a preset pattern and a via at a bottom of the trench, a Cu wiring by burying Cu or Cu alloy in the trench and the via includes forming a barrier film (process 2); forming, on a surface of the barrier film, a wetting target layer of Ru or the like (process 3); forming, on a surface of the wetting target layer, a Cu-based seed film by PVD (process 4); filling the via by heating the substrate and flowing the Cu-based seed film into the via (process 5); and forming, on the substrate surface, a Cu-based film made of the Cu or Cu alloy by PVD under a condition where the Cu-based film is flown on the wetting target layer to bury the Cu-based film in the trench (process 6).