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公开(公告)号：US06954371B2
公开(公告)日：2005-10-11
申请号：US10860770
申请日：2004-06-04
IPC分类号： H01L27/108 , G11C7/06 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/4099 , H01L21/8242 , G11C11/24 , G11C7/00 , G11C7/02
CPC分类号： H01L27/10897 , G11C7/062 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C2207/2227 , H01L27/10814
摘要： The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout. In a memory array including a plurality of memory cells having capacitors which are formed corresponding to a plurality of word lines and a plurality of bit lines, stored information of the memory cell which is read to one bit line out of the pair of bit lines is sensed by a sense amplifier in response to a reference voltage which is formed by a dummy cell connected to another bit line, a precharge voltage of high level or low level corresponding to an operational voltage by a precharge circuit is supplied to the bit lines, and the dummy cells having the same structure as the memory cells are formed at crossing points of word lines for dummy cells and bit lines arranged outside the memory array, MOSFETs which precharge an intermediate voltage between the high level voltage and the low level voltage to the capacitors are provided, and gates of the MOSFETs are connected with charge word lines for dummy cells which are extended in parallel with the word lines for dummy cells.
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公开(公告)号：US06795358B2
公开(公告)日：2004-09-21
申请号：US10459625
申请日：2003-06-12
IPC分类号： G11C700
CPC分类号： H01L27/10882 , G11C7/065 , G11C7/1042 , G11C7/12 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/2227 , H01L27/0207 , H01L27/108 , H01L27/10885 , H01L27/10891
摘要： Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.
摘要翻译： 这里公开了一种配备有存储电路的半导体集成电路装置，其以简单的配置实现其操作的加速和低功耗。 在包括用于响应于操作定时信号执行放大操作的CMOS锁存电路的读出放大器的输入/输出节点处，一对第一预充电MOSFET在预充电期间变为导通状态，从而提供预充电电压，以及 提供了用于连接输入/输出节点和响应于选择信号的每个互补位线对的选择开关MOSFET。 在互补位线对之间提供用于短路互补位线对的第二预充电MOSFET。 提供了一种存储器阵列，其包括每个包括地址选择MOSFET和存储电容器的动态存储器单元，每个存储器单元设置在互补位线对之一和与其相交的字线之间。 与用于选择MOSFET的栅极绝缘膜相比，用于第二预充电MOSFET的栅极绝缘膜的厚度形成得较薄。
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公开(公告)号：US20060050583A1
公开(公告)日：2006-03-09
申请号：US11262920
申请日：2005-11-01
IPC分类号： G11C7/00
CPC分类号： H01L27/10882 , G11C7/065 , G11C7/1042 , G11C7/12 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/2227 , H01L27/0207 , H01L27/108 , H01L27/10885 , H01L27/10891
摘要： Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.
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4.发明授权公开(公告)号：US06977856B2
公开(公告)日：2005-12-20
申请号：US10914291
申请日：2004-08-10
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C11/409 , G11C11/4091 , G11C11/4094 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10882 , G11C7/065 , G11C7/1042 , G11C7/12 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/2227 , H01L27/0207 , H01L27/108 , H01L27/10885 , H01L27/10891
摘要： Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.
摘要翻译： 这里公开了一种配备有存储电路的半导体集成电路装置，其以简单的配置实现其操作的加速和低功耗。 在包括用于响应于操作定时信号执行放大操作的CMOS锁存电路的读出放大器的输入/输出节点处，一对第一预充电MOSFET在预充电期间变为导通状态，从而提供预充电电压，以及 提供了用于连接输入/输出节点和响应于选择信号的每个互补位线对的选择开关MOSFET。 在互补位线对之间提供用于短路互补位线对的第二预充电MOSFET。 提供了一种存储器阵列，其包括每个包括地址选择MOSFET和存储电容器的动态存储器单元，每个存储器单元设置在互补位线对之一和与其相交的字线之间。 与用于选择MOSFET的栅极绝缘膜相比，用于第二预充电MOSFET的栅极绝缘膜的厚度形成得较薄。
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公开(公告)号：US20050265096A1
公开(公告)日：2005-12-01
申请号：US11136510
申请日：2005-05-25
IPC分类号： H01L27/108 , G11C7/00 , G11C7/12 , G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/105
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译： 提供了其操作加快并且功耗降低的DRAM。 提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。
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公开(公告)号：US20050007846A1
公开(公告)日：2005-01-13
申请号：US10914291
申请日：2004-08-10
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C11/409 , G11C11/4091 , G11C11/4094 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , G11C7/00
CPC分类号： H01L27/10882 , G11C7/065 , G11C7/1042 , G11C7/12 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/2227 , H01L27/0207 , H01L27/108 , H01L27/10885 , H01L27/10891
摘要： Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.
摘要翻译： 这里公开了一种配备有存储电路的半导体集成电路装置，其以简单的配置实现其操作的加速和低功耗。 在包括用于响应于操作定时信号执行放大操作的CMOS锁存电路的读出放大器的输入/输出节点处，一对第一预充电MOSFET在预充电期间变为导通状态，从而提供预充电电压，以及 提供了用于连接输入/输出节点和响应于选择信号的每个互补位线对的选择开关MOSFET。 在互补位线对之间提供用于短路互补位线对的第二预充电MOSFET。 提供了一种存储器阵列，其包括每个包括地址选择MOSFET和存储电容器的动态存储器单元，每个存储器单元设置在互补位线对之一和与其相交的字线之间。 与用于选择MOSFET的栅极绝缘膜相比，用于第二预充电MOSFET的栅极绝缘膜的厚度形成得较薄。
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公开(公告)号：US07440350B2
公开(公告)日：2008-10-21
申请号：US11708348
申请日：2007-02-21
CPC分类号： G11C7/12 , G11C2207/005 , H01L27/105 , H01L27/10897
摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
摘要翻译： 提供了其操作加快并且功耗降低的DRAM。 提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。
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8.发明授权公开(公告)号：US07177215B2
公开(公告)日：2007-02-13
申请号：US11262920
申请日：2005-11-01
IPC分类号： G11C7/12
CPC分类号： H01L27/10882 , G11C7/065 , G11C7/1042 , G11C7/12 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/2227 , H01L27/0207 , H01L27/108 , H01L27/10885 , H01L27/10891
摘要： A semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption in a simple configuration is provided. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.
摘要翻译： 提供了一种配备有存储电路的半导体集成电路器件，其实现了其简单配置中其操作的加速和低功耗。 在包括用于响应于操作定时信号执行放大操作的CMOS锁存电路的读出放大器的输入/输出节点处，一对第一预充电MOSFET在预充电周期期间变为导通状态以提供预充电电压，并且选择 提供了用于响应于选择信号连接输入/输出节点和每个互补位线对的开关MOSFET。 在互补位线对之间提供用于短路互补位线对的第二预充电MOSFET。 提供了一种存储器阵列，其包括每个包括地址选择MOSFET和存储电容器的动态存储器单元，每个存储器单元设置在互补位线对之一和与其相交的字线之间。 与用于选择MOSFET的栅极绝缘膜相比，用于第二预充电MOSFET的栅极绝缘膜的厚度形成得较薄。
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公开(公告)号：US07145792B2
公开(公告)日：2006-12-05
申请号：US11211543
申请日：2005-08-26
CPC分类号： H01L27/10897 , G11C7/062 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C2207/2227 , H01L27/10814
摘要： The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout. In a memory array including a plurality of memory cells having capacitors which are formed corresponding to a plurality of word lines and a plurality of bit lines, stored information of the memory cell which is read to one bit line out of the pair of bit lines is sensed by a sense amplifier in response to a reference voltage which is formed by a dummy cell connected to another bit line, a precharge voltage of high level or low level corresponding to an operational voltage by a precharge circuit is supplied to the bit lines, and the dummy cells having the same structure as the memory cells are formed at crossing points of word lines for dummy cells and bit lines arranged outside the memory array, MOSFETs which precharge an intermediate voltage between the high level voltage and the low level voltage to the capacitors are provided, and gates of the MOSFETs are connected with charge word lines for dummy cells which are extended in parallel with the word lines for dummy cells.
摘要翻译： 本发明提供一种动态RAM，其可以在低电压下操作，并且实现读取余量和区域节省布局的增强。 在包括多个存储单元的存储器阵列中，所述多个存储单元具有对应于多个字线和多个位线形成的电容器，从该位线对中读出的一个位线的存储单元的存储信息是 由读出放大器响应由连接到另一位线的虚拟单元形成的参考电压而感测到的，由预充电电路对应于操作电压的高电平或低电平的预充电电压被提供给位线，并且 具有与存储单元相同结构的虚拟单元形成在用于存储阵列外部的虚设单元和位线的字线的交叉点处，将高电平电压和低电平电压之间的中间电压预充电到电容器 并且MOSFET的栅极与用于虚拟单元的字线平行延伸的虚拟单元的充电字线连接。
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公开(公告)号：US20050024949A1
公开(公告)日：2005-02-03
申请号：US10860770
申请日：2004-06-04
IPC分类号： H01L27/108 , G11C7/06 , G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/4099 , H01L21/8242 , G11C5/00
CPC分类号： H01L27/10897 , G11C7/062 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/4099 , G11C2207/2227 , H01L27/10814
摘要： The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout. In a memory array including a plurality of memory cells having capacitors which are formed corresponding to a plurality of word lines and a plurality of bit lines, stored information of the memory cell which is read to one bit line out of the pair of bit lines is sensed by a sense amplifier in response to a reference voltage which is formed by a dummy cell connected to another bit line, a precharge voltage of high level or low level corresponding to an operational voltage by a precharge circuit is supplied to the bit lines, and the dummy cells having the same structure as the memory cells are formed at crossing points of word lines for dummy cells and bit lines arranged outside the memory array, MOSFETs which precharge an intermediate voltage between the high level voltage and the low level voltage to the capacitors are provided, and gates of the MOSFETs are connected with charge word lines for dummy cells which are extended in parallel with the word lines for dummy cells.
摘要翻译： 本发明提供一种动态RAM，其可以在低电压下操作，并且实现读取余量和区域节省布局的增强。 在包括多个存储单元的存储器阵列中，所述多个存储单元具有对应于多个字线和多个位线形成的电容器，从该位线对中读出的一个位线的存储单元的存储信息是 由读出放大器响应由连接到另一位线的虚拟单元形成的参考电压而感测到的，由预充电电路对应于操作电压的高电平或低电平的预充电电压被提供给位线，并且 具有与存储单元相同结构的虚拟单元形成在用于存储阵列外部的虚设单元和位线的字线的交叉点处，将高电平电压和低电平电压之间的中间电压预充电到电容器 并且MOSFET的栅极与用于虚拟单元的字线平行延伸的虚拟单元的充电字线连接。
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