公开(公告)号：US5100814A

公开(公告)日：1992-03-31

申请号：US628007

申请日：1990-12-17

申请人： Hiroshi Yamaguchi ,  Masao Yoshizawa ,  Kazumasa Satsuma ,  Takeshi Kida ,  Tomohide Terashima

发明人： Hiroshi Yamaguchi ,  Masao Yoshizawa ,  Kazumasa Satsuma ,  Takeshi Kida ,  Tomohide Terashima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/78

CPC分类号： H01L21/76297 ,  H01L27/0623 ,  Y10S148/135

摘要： First and second semiconductor elements are formed in first and second semiconductor element forming regions which have the same thickness, include first and second semiconductor layers and are separated with dielectric isolation from each other. The thickness of the first semiconductor layer is made different between the first and second semiconductor element forming regions, so that the thickness of the second semiconductor layer becomes different between the first and second semiconductor element forming regions. Thus, the semiconductor device may have the semiconductor elements which have second semiconductor layers with different thicknesses in accordance with desired electrical characteristics for each of the semiconductor elements formed in the first and second semiconductor element forming regions, to complement a semiconductor device having the semiconductor elements each of which has independent optimum electrical characteristics.

摘要翻译： 第一和第二半导体元件形成在具有相同厚度的第一和第二半导体元件形成区域中，包括第一和第二半导体层并且彼此隔开隔离。 在第一和第二半导体元件形成区域之间使第一半导体层的厚度不同，使得第一半导体元件形成区域和第二半导体元件形成区域之间的第二半导体层的厚度变得不同。 因此，半导体器件可以具有根据形成在第一和第二半导体元件形成区域中的每个半导体元件的所需电特性而具有不同厚度的第二半导体层的半导体元件，以补充具有半导体元件的半导体器件 每个都具有独立的最佳电气特性。

公开(公告)号：US5200638A

公开(公告)日：1993-04-06

申请号：US547243

申请日：1990-07-03

申请人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

发明人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732 ,  H01L29/735 ,  H01L29/739 ,  H01L29/745 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/404 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7455 ,  H01L29/7826 ,  H01L29/8611

摘要： On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.31 epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer. The potential of the p floating region is determined by capacity coupling in the current blocking state and thus the sense voltage characteristics through the sense electrode can be smooth.

公开(公告)号：US5455439A

公开(公告)日：1995-10-03

申请号：US329052

申请日：1994-10-26

申请人： Tomohide Terashima ,  Kazumasa Satsuma ,  Masao Yoshizawa

发明人： Tomohide Terashima ,  Kazumasa Satsuma ,  Masao Yoshizawa

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L29/06 ,  H01L29/40 ,  H01L23/535

CPC分类号： H01L29/404

摘要： The present invention relates to a semiconductor device which is fabricated in simple process steps and which prevents deterioration in a breakdown voltage. Two diffusion regions are formed in space in a surface of an n.sup.- type layer. The diffusion regions are separated from each other by an insulation layer, but each in contact with a conductive film. Another conductive film is disposed on the insulation layer. The three conductive films are insulated from each other by the insulation layer and still another overlying insulation layer. Still other conductive films are formed on the upper insulation layer, and are coupled to the three conductive films. A wiring conductive film is also formed on the upper insulation layer. The wiring conductive film has a relatively small capacitance with the three conductive films. Due to the device structure, influence of the wiring conductive film over the surface of the semiconductor device is blocked by the conductive films. Hence, an electric field concentration will not result.

摘要翻译： 本发明涉及以简单的工艺步骤制造并防止击穿电压劣化的半导体器件。 在n型层的表面的空间中形成两个扩散区域。 扩散区域通过绝缘层彼此分离，但各自与导电膜接触。 另一导电膜设置在绝缘层上。 三个导电膜通过绝缘层和另一个上覆绝缘层彼此绝缘。 其它导电膜形成在上绝缘层上，并与三个导电膜耦合。 布线导电膜也形成在上绝缘层上。 布线导电膜与三个导电膜具有相对较小的电容。 由于器件结构，导电膜在半导体器件的表面上的影响被导电膜阻挡。 因此，不会产生电场浓度。

公开(公告)号：US5279977A

公开(公告)日：1994-01-18

申请号：US997924

申请日：1992-12-29

申请人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

发明人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732 ,  H01L29/735 ,  H01L29/739 ,  H01L29/745 ,  H01L29/78 ,  H01L29/861 ,  H01L21/265

CPC分类号： H01L29/404 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7455 ,  H01L29/7826 ,  H01L29/8611

摘要： On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer. The potential of the p floating region is determined by capacity coupling in the current blocking state and thus the sense voltage characteristics through the sense electrode can be smooth.

摘要翻译： 在p-衬底上，n型外延层由p阱包围和隔离。 在n外延层的表面中，在p阱附近提供p浮置区，在其上设置感测电极。 绝缘膜和导电膜形成在p阱和p浮动区之间的n外延层上以重叠。 导电膜和p浮动区域用作复合场板，这使得表面电场分布受表面电荷状态的影响很困难，通过扩展耗尽层来减轻表面电场，延伸 从n-外延层和p阱之间的pn结到电流阻挡状态的n-外延层朝向n-外延层的中心。 p浮动区域的电位由电流阻塞状态下的电容耦合决定，因此通过感测电极的感测电压特性可以是平滑的。

公开(公告)号：US5258641A

公开(公告)日：1993-11-02

申请号：US944074

申请日：1992-09-11

申请人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

发明人： Takeshi Kida ,  Kazumasa Satsuma ,  Gourab Majumdar ,  Tomohide Terashima ,  Hiroshi Yamaguchi ,  Masanori Fukunaga ,  Masao Yoshizawa

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/735 ,  H01L29/739 ,  H01L29/745 ,  H01L29/78 ,  H01L29/861 ,  H01L29/68

CPC分类号： H01L29/404 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7455 ,  H01L29/7826 ,  H01L29/8611

摘要： On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer. The potential of the p floating region is determined by capacity coupling in the current blocking state and thus the sense voltage characteristics through the sense electrode can be smooth.

摘要翻译： 在p-衬底上，n型外延层由p阱包围和隔离。 在n外延层的表面中，在p阱附近提供p浮置区，在其上设置感测电极。 绝缘膜和导电膜形成在p阱和p浮动区之间的n外延层上以重叠。 导电膜和p浮动区域用作复合场板，这使得表面电场分布受表面电荷状态的影响很困难，通过扩展耗尽层来减轻表面电场，延伸 从n-外延层和p阱之间的pn结到电流阻挡状态的n-外延层朝向n-外延层的中心。 p浮动区域的电位由电流阻塞状态下的电容耦合决定，因此通过感测电极的感测电压特性可以是平滑的。

公开(公告)号：US5574303A

公开(公告)日：1996-11-12

申请号：US325633

申请日：1994-10-19

申请人： Tomohide Terasima ,  Mituharu Tabata ,  Masao Yoshizawa ,  Kazumasa Satsuma

发明人： Tomohide Terasima ,  Mituharu Tabata ,  Masao Yoshizawa ,  Kazumasa Satsuma

IPC分类号： H01L21/66 ,  G01R19/00 ,  H01L29/06 ,  H01L29/735 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94

CPC分类号： G01R19/0084 ,  H01L29/0692 ,  H01L29/735 ,  H01L29/7392

摘要： The present invention provides a semiconductor device which is excellent in voltage sense characteristic and simple in manufacturing process. P diffusion regions 12 and 13 are selectively formed on a first major surface of an N.sup.- substrate 11, an electrode 31 is formed on the P diffusion region, a sense electrode 32 is formed on the P diffusion region 13, and an electrode 33 is formed on a second major surface of the N.sup.- substrate. Then, the electrode 31 is set at 0 V, constant current is led to the sense electrode 32, and the electrode 33 is positively biased. Thus, the voltage applied to the electrode 33 is sensed from a potential obtained at the sense electrode 32. A distance between the P diffusion regions 12 and 13 which determines a voltage sense characteristic can be accurately controlled, and a good voltage sense characteristic can be obtained. Moreover, a manufacturing process is relatively simple.

摘要翻译： 本发明提供一种电压检测特性优异且制造工艺简单的半导体器件。 P扩散区12和13选择性地形成在N基板11的第一主表面上，在P扩散区上形成电极31，在P扩散区13上形成感测电极32，电极33 形成在N-底物的第二主表面上。 然后，将电极31设定为0V，将恒定电流引导到感测电极32，并且电极33被正偏置。 因此，从感测电极32获得的电位感测施加到电极33的电压。可以精确地控制确定电压感测特性的P扩散区域12和13之间的距离，并且可以获得良好的电压感测特性 获得。 此外，制造过程相对简单。

公开(公告)号：US5489793A

公开(公告)日：1996-02-06

申请号：US272285

申请日：1994-07-08

申请人： Takuo Matsusako ,  Kazumasa Satsuma

发明人： Takuo Matsusako ,  Kazumasa Satsuma

IPC分类号： H01L21/66 ,  G01R31/28 ,  G01R31/316 ,  H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L23/62 ,  H01L23/48 ,  H01L23/52

CPC分类号： G01R31/316 ,  H01L27/0207

摘要： There are provided a plurality of standard cell blocks (2) within an IC chip (1), and an aluminium wiring layer is formed in an aluminium wiring region (8) provided between the standard cell blocks (2) to electrically connect the standard cell blocks (2) to each other. An n-type epitaxial region (4), a p-type diffusion region (5) and an n-type diffusion region (6) are incorporated in an underlayer of the aluminium wiring region (8), to thereby form an evaluation device which is an npn bipolar transistor under the aluminium wiring region (8). A semiconductor device which is capable of accurately evaluating its finished product by the inspection of the evaluation device is provided without the damage of an integration level.

摘要翻译： 在IC芯片（1）内设置有多个标准单元块（2），并且在设置在标准单元块（2）之间的铝布线区域（8）中形成铝布线层，以电连接标准单元 块（2）彼此。 在铝布线区域（8）的底层中并入n型外延区域（4），p型扩散区域（5）和n型扩散区域（6），从而形成评价装置， 是在铝布线区域（8）下面的npn双极晶体管。 提供能够通过评估装置的检查对其成品进行精确评价的半导体装置，而不会造成集成度的损害。