公开(公告)号：US09299629B2

公开(公告)日：2016-03-29

申请号：US12932560

申请日：2011-02-28

申请人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

发明人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

IPC分类号： H01L21/78 ,  H01L23/29 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L23/293 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.

摘要翻译： 半导体器件具有设置有划线区域和IC区域的半导体衬底。 第一绝缘膜设置在跨越划线区域和IC区域的半导体衬底上。 在划线区域的第一绝缘膜中设置至少一个分隔槽。 由插塞金属膜制成的侧壁仅形成在分隔槽的相应侧壁上，使得侧壁上的插塞金属膜不会从分离槽延伸出来，并且不存在于第一绝缘膜的上表面上 。 第二绝缘膜至少覆盖形成在分隔槽的各个侧壁上的侧壁，使得侧壁设置在第二绝缘膜下方。

公开(公告)号：US08324687B2

公开(公告)日：2012-12-04

申请号：US12695443

申请日：2010-01-28

申请人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

发明人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

IPC分类号： H01L23/62

CPC分类号： H01L23/62 ,  H01L27/0259 ,  H01L27/027 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/423 ,  H01L29/735 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

摘要翻译： 提供一种半导体器件，包括：在半导体衬底的表面上形成的PW层; 形成在所述半导体衬底的与所述PW层接触的表面的NW层; 形成在PW层中的半导体衬底的表面的p +基层; 形成在所述NW层的半导体衬底的表面的n +集电体层; 位于p +基极层和n +集电极层之间并形成在PW层中的半导体衬底的表面的n +发射极层; 以及形成在n +集电极层和PW层之间的与n +集电极层接触的n +层。

公开(公告)号：US20110221043A1

公开(公告)日：2011-09-15

申请号：US12932560

申请日：2011-02-28

申请人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

发明人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

IPC分类号： H01L23/544 ,  H01L21/28

CPC分类号： H01L23/293 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region (003) and an IC region (004). At least one separation groove (007) is provide in an inter-layer insulating film (002) in the scribe region 003, and a side wall (011) made of a plug metal film is formed on each lateral wall of the separation groove (007). A passivation film is provided to cover at least the side walls (011).

摘要翻译： 提供一种半导体装置，其适用于防止由于切割而导致的膜剥离并防止异常放电。 半导体器件包括划线区（003）和IC区（004）。 在划线区域003中的层间绝缘膜（002）中设置至少一个分离槽（007），并且在分隔槽的每个侧壁上形成由插塞金属膜制成的侧壁（011） 007）。 提供钝化膜以至少覆盖侧壁（011）。

公开(公告)号：US20100187608A1

公开(公告)日：2010-07-29

申请号：US12695443

申请日：2010-01-28

申请人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

发明人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

IPC分类号： H01L29/06 ,  H01L29/73 ,  H01L29/78

CPC分类号： H01L23/62 ,  H01L27/0259 ,  H01L27/027 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/423 ,  H01L29/735 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

摘要翻译： 提供一种半导体器件，包括：在半导体衬底的表面上形成的PW层; 形成在所述半导体衬底的与所述PW层接触的表面的NW层; 形成在PW层中的半导体衬底的表面的p +基层; 形成在所述NW层的半导体衬底的表面的n +集电体层; 位于p +基极层和n +集电极层之间并形成在PW层中的半导体衬底的表面的n +发射极层; 以及形成在n +集电极层和PW层之间的与n +集电极层接触的n +层。

公开(公告)号：US08803231B2

公开(公告)日：2014-08-12

申请号：US13438058

申请日：2012-04-03

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/785

摘要： Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

摘要翻译： 沟槽部分（10）形成在井（5）中，以便在井（5）中提供不均匀性。 在沟槽部分（10）的上表面和内部经由绝缘膜（7）形成栅电极（2）。 源极区域（3）以栅极长度方向形成在栅电极（2）的一侧，而另一侧的漏极区域（4）形成。 源极区域（3）和漏极区域（4）都形成为靠近栅电极（2）的底部附近。 通过深深地形成源极区域（3）和漏极区域（4），电流均匀地流过整个沟槽部分（10），并且在阱（5）中形成的凹凸增加了有效栅极宽度以降低导通电阻 并提高其驱动能力。

公开(公告)号：US08168494B2

公开(公告)日：2012-05-01

申请号：US12027655

申请日：2008-02-07

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/785

摘要： Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

摘要翻译： 沟槽部分（10）形成在井（5）中，以便在井（5）中提供不均匀性。 在沟槽部分（10）的上表面和内部经由绝缘膜（7）形成栅电极（2）。 源极区域（3）以栅极长度方向形成在栅电极（2）的一侧，而另一侧的漏极区域（4）形成。 源极区域（3）和漏极区域（4）都形成为靠近栅电极（2）的底部附近。 通过深深地形成源极区域（3）和漏极区域（4），电流均匀地流过整个沟槽部分（10），并且在阱（5）中形成的凹凸增加了有效栅极宽度以降低导通电阻 并提高其驱动能力。

公开(公告)号：US20100289078A1

公开(公告)日：2010-11-18

申请号：US12733191

申请日：2008-08-20

申请人： Tomomitsu Risaki

发明人： Tomomitsu Risaki

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851

摘要： In order to further improve a driving performance without increasing an element area in a lateral MOS having a high driving performance, in which a gate width is increased per unit area by forming a plurality of trenches horizontally with respect to a gate length direction, the semiconductor device includes: a well region which is formed of a high resistance first conductivity type semiconductor at a predetermined depth from a surface of a semiconductor substrate; a plurality of trenches which extend from a surface to a midway depth in the well region; a gate insulating film which is formed on surfaces of concave and convex portions formed by the trenches; a gate electrode embedded inside the trenches; a gate electrode film which is formed on the surface of the substrate in contact with the gate electrode embedded inside the trenches in regions of the concave and convex portions, the regions excluding vicinities of both ends of the trenches; another gate electrode film which is embedded inside the trenches in the vicinities of the both ends of the trenches in contact with the gate electrode film so that a surface of the another gate electrode film is located at a position deeper than the surface of the semiconductor substrate; and a source region and a drain region which are formed as two low resistance second conductivity type semiconductor layers formed from a part of the semiconductor surface, the part being out of contact with the another gate electrode film, so as to be shallower than the depth of the well region.

摘要翻译： 为了进一步提高驱动性能，而不增加具有高驱动性能的横向MOS元件区域，其中通过相对于栅极长度方向水平形成多个沟槽，每单位面积的栅极宽度增加，半导体 器件包括：阱区，其由距半导体衬底的表面预定深度的高电阻第一导电型半导体形成; 多个沟槽，其在井区域中从表面延伸到中间深度; 形成在由沟槽形成的凹部和凸部的表面上的栅极绝缘膜; 埋在沟槽内的栅电极; 栅极电极膜，其形成在与所述凹部和凸部的区域中嵌入在所述沟槽内的所述栅极电极接触的所述基板的表面上，所述沟槽的两端的附近不包括所述区域; 埋入沟槽两端附近的与栅极电极膜接触的沟槽内的另一个栅极电极膜，使得另一栅极电极膜的表面位于比半导体衬底的表面更深的位置 ; 以及形成为由半导体表面的一部分形成的两个低电阻第二导电类型半导体层的源极区和漏极区，该部分与另一个栅电极膜不接触，以便比深度 的井区。

公开(公告)号：US08193060B2

公开(公告)日：2012-06-05

申请号：US12949434

申请日：2010-11-18

申请人： Tomomitsu Risaki

发明人： Tomomitsu Risaki

IPC分类号： H01L21/336

CPC分类号： H01L29/41766 ,  H01L29/0882 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7813 ,  H01L29/7825 ,  H01L29/7827

摘要： Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state.

摘要翻译： 提供一种半导体器件的制造方法。 形成在半导体基板上的阱区域包括多个沟槽区域，源电极连接到形成在沟槽区域之间的衬底表面上的源极区域。 形成与源极区域相邻的高浓度区域，与源极区域一起与源极电极对接，由此固定基板电位。 漏极区域形成在沟槽区域的底部，其电位通过埋在沟槽区域内的漏电极而被带到衬底表面。 对栅电极和漏电极施加任意电压，由此载流子从源极区域流到漏极区域，并且半导体器件处于导通状态。

公开(公告)号：US07888212B2

公开(公告)日：2011-02-15

申请号：US12392450

申请日：2009-02-25

申请人： Tomomitsu Risaki ,  Yuichiro Kitajima

发明人： Tomomitsu Risaki ,  Yuichiro Kitajima

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835

摘要： In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.

摘要翻译： 在阱区域中，在栅极宽度方向上形成不规则结构，并且通过绝缘膜在凹部和凸部的上表面上形成栅电极。 在栅极长度方向的一侧形成上下源极区，在另一侧形成上下漏极区。 因此，通过在源极和漏极区域形成下部源极和漏极区域，可以抑制在栅极长度变短时产生的沟道区域的上部产生的电流集中，并且可以使电流均匀地流动 在整个沟道区域中，由于在阱区域中形成不规则结构，因此使有效栅极宽度变宽。 因此，减小了半导体器件的导通电阻以提高驱动性能。

公开(公告)号：US07768102B2

公开(公告)日：2010-08-03

申请号：US11404934

申请日：2006-04-14

申请人： Tomomitsu Risaki

发明人： Tomomitsu Risaki

IPC分类号： H01L29/06

CPC分类号： H01L29/7802 ,  H01L24/32 ,  H01L24/83 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/41766 ,  H01L29/7813 ,  H01L2224/13016 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81903 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor chip having a rear surface provided with an uneven structure having a preselected pattern and comprised of concave and convex portions. The preselected pattern of the uneven structure is tilted so as to be in parallel to a crystal orientation of of the semiconductor chip. An electrode is disposed on the concave and convex portions of the uneven structure.

摘要翻译： 半导体器件包括半导体芯片，其具有设置有具有预选图案且由凹凸部分组成的不均匀结构的后表面。 不平坦结构的预选图案被倾斜以与半导体芯片的<110>的晶体取向平行。 电极设置在凹凸结构的凹凸部上。