公开(公告)号：US07375399B2

公开(公告)日：2008-05-20

申请号：US11156558

申请日：2005-06-21

申请人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

发明人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C2207/104 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116

摘要： The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.

摘要翻译： 本发明是具有在同一芯片上的逻辑块和存储器块的半导体存储器件。 在存储器件中，单元存储单元每个都包括至少两个晶体管，其中之一是用于存储电荷并将其从电荷存储节点释放的写入晶体管，另一个是在沟道中的电导 读取晶体管的源极和漏极之间的区域被调制，取决于由写入晶体管存储或从电荷存储节点释放的电荷的量。 读取晶体管具有比设置在逻辑块中的晶体管更厚的栅极绝缘膜，并且使用与逻辑块相同的扩散层结构。

公开(公告)号：US20080261357A1

公开(公告)日：2008-10-23

申请号：US11956858

申请日：2007-12-14

申请人： Norifumi KAMESHIRO ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

发明人： Norifumi KAMESHIRO ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

IPC分类号： H01L21/84

CPC分类号： H01L29/66757 ,  H01L29/66613 ,  H01L29/66772

摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.

摘要翻译： 在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。 然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。 此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。 随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。 然后，在源极 - 漏极材料膜上形成掩模层。 接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。 一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

公开(公告)号：US08106449B2

公开(公告)日：2012-01-31

申请号：US11493688

申请日：2006-07-27

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Norifumi Kameshiro ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Norifumi Kameshiro ,  Toshiyuki Mine

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11 ,  H01L27/11517 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/78

摘要： To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.

摘要翻译： 为了在具有增益单元结构的存储单元中实现稳定的读取操作，构造了写入晶体管，其具有形成在绝缘层上的源极和漏极，形成在绝缘层上并且在源极和 所述漏极由半导体构成，栅极形成在所述绝缘层的上部，所述源极与漏极之间，并且通过栅极绝缘膜与所述沟道电绝缘并控制所述沟道的电位。 通道将源极和漏极的侧表面上的源极和漏极电连接。

公开(公告)号：US07772053B2

公开(公告)日：2010-08-10

申请号：US11956858

申请日：2007-12-14

申请人： Norifumi Kameshiro ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

发明人： Norifumi Kameshiro ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

IPC分类号： H01L21/00

CPC分类号： H01L29/66757 ,  H01L29/66613 ,  H01L29/66772

摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.

摘要翻译： 在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。 然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。 此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。 随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。 然后，在源极 - 漏极材料膜上形成掩模层。 接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。 一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

公开(公告)号：US20070063287A1

公开(公告)日：2007-03-22

申请号：US11493688

申请日：2006-07-27

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Norifumi Kameshiro ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Norifumi Kameshiro ,  Toshiyuki Mine

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11 ,  H01L27/11517 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/78

摘要： To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.

摘要翻译： 为了在具有增益单元结构的存储单元中实现稳定的读取操作，构造了写入晶体管，其具有形成在绝缘层上的源极和漏极，形成在绝缘层上并且在源极和 所述漏极由半导体构成，栅极形成在所述绝缘层的上部，所述源极与漏极之间，并且通过栅极绝缘膜与所述沟道电绝缘并控制所述沟道的电位。 通道将源极和漏极的侧表面上的源极和漏极电连接。

公开(公告)号：US20050280000A1

公开(公告)日：2005-12-22

申请号：US11156558

申请日：2005-06-21

申请人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

发明人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

IPC分类号： G11C11/405 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11 ,  H01L29/10

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C2207/104 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116

摘要： The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.

摘要翻译： 本发明是具有在同一芯片上的逻辑块和存储器块的半导体存储器件。 在存储器件中，单元存储单元每个都包括至少两个晶体管，其中之一是用于存储电荷并将其从电荷存储节点释放的写入晶体管，另一个是在沟道中的电导 读取晶体管的源极和漏极之间的区域被调制，取决于由写入晶体管存储或从电荷存储节点释放的电荷的量。 读取晶体管具有比设置在逻辑块中的晶体管更厚的栅极绝缘膜，并且使用与逻辑块相同的扩散层结构。

公开(公告)号：US06194759B1

公开(公告)日：2001-02-27

申请号：US09436225

申请日：1999-11-09

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L2976

CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888

摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

公开(公告)号：US6040605A

公开(公告)日：2000-03-21

申请号：US236630

申请日：1999-01-26

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  G11C2216/08

摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

公开(公告)号：USRE41868E1

公开(公告)日：2010-10-26

申请号：US11708145

申请日：2007-02-20

申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  H01L29/7889

摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

公开(公告)号：US07468901B2

公开(公告)日：2008-12-23

申请号：US11399397

申请日：2006-04-07

申请人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

发明人： Norifumi Kameshiro ,  Riichiro Takemura ,  Tomoyuki Ishii

IPC分类号： G11C7/00

CPC分类号： G11C11/405 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/108

摘要： In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.

摘要翻译： 在双晶体管增益单元结构中，提供了能够稳定读取而没有故障并且具有小面积存储单元的半导体存储器件。 在具有写晶体管和读晶体管的双晶体管增益单元存储器中，分别提供写字线，读字线，写位线和读位线，并且独立地设置要施加的电压。 此外，存储单元连接到与相邻存储单元相同的读字线和写位线。