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    Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove
    1.
    发明授权
    Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove 失效
    在公共衬底上形成的半导体集成电路器件通过由沟槽隔离的场氧化物和双极晶体管隔离的MISFET

    公开(公告)号：US5214302A

    公开(公告)日：1993-05-25

    申请号：US807411

    申请日：1991-12-13

    申请人： Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

    发明人： Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

    IPC分类号： H01L27/06 ,  H01L27/11 ,  H01L29/732

    CPC分类号： H01L29/7325 ,  H01L27/0623 ,  H01L27/1112

    摘要： A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.

    摘要翻译： 一种半导体集成电路器件，具有以下结构，其中以下各个区域，即用于形成每个双极晶体管的基极和发射极区域的第一区域，用于形成双极性的集电极导出区域的第二区域 晶体管和用于形成每个MISFET的第三区域从半导体衬底的主表面突出，由此可以实现MISFET之间以及这些MISFET与具有相同隔离结构的双极晶体管之间的隔离，并且在 与双极晶体管之间的隔离相同的制造步骤。 此外，在该器件中，双极晶体管的基极区域电自自对准地连接到形成在主表面上以围绕发射极区域的基极。 双极晶体管的特征在于自对准晶体管，并且与栅极和基极（发射极）电极对应的绝缘侧壁间隔物由相同的杆形成。

    Method of making semiconductor integrated circuit device
    6.
    发明授权
    Method of making semiconductor integrated circuit device 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US4219369A

    公开(公告)日：1980-08-26

    申请号：US931007

    申请日：1978-08-04

    申请人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

    发明人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

    IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/388 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/26

    CPC分类号： H01L21/388 ,  H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/76216 ,  H01L21/76232 ,  H01L21/8222 ,  Y10S148/117 ,  Y10S148/143

    摘要： The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.

    摘要翻译： 本发明涉及一种制造半导体集成电路器件的方法，其目的在于减小将相邻半导体元件彼此隔离的隔离区的尺寸。 本发明的方法具有以下步骤：在衬底上形成不同导电类型的扩散杂质的沉积层与衬底的沉积层，在沉积层上形成具有孔的掩模膜，通过使用掩模膜进行蚀刻 作为扩散掩模，以蚀刻沉积层和基板下面的部分，从而形成将沉积层分成岛状沉积层部分的凹槽，并且将每个岛状沉积层中的杂质拉伸和扩散 沉积层部分以形成构成半导体元件的一部分的扩散层。