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    Semiconductor memory for serial data access
    1.
    发明授权
    Semiconductor memory for serial data access 失效
    用于串行数据访问的半导体存储器

    公开(公告)号：US4701884A

    公开(公告)日：1987-10-20

    申请号：US896257

    申请日：1986-08-14

    申请人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

    发明人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

    IPC分类号： G11C11/56 ,  H01L27/108 ,  G11C13/00

    CPC分类号： G11C11/565 ,  H01L27/10805

    摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.

    摘要翻译： 提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据 提供写入和数据读取机制。 该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上 并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构 提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

    Semiconductor memory having multiple level storage structure
    2.
    发明授权
    Semiconductor memory having multiple level storage structure 失效
    具有多级存储结构的半导体存储器

    公开(公告)号：US4661929A

    公开(公告)日：1987-04-28

    申请号：US686018

    申请日：1984-12-24

    申请人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    发明人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    IPC分类号： G06F11/10 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/40

    CPC分类号： G11C11/565 ,  G11C11/4091 ,  G11C7/065 ,  G06F11/1072 ,  G11C29/00 ,  G11C7/06

    摘要： In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

    摘要翻译： 在半导体存储器中，包括由分别具有至少一个存储电容器的多个存储器单元组成的存储器阵列，指定每个存储单元的位置的寻址电路，发送连接到所述存储单元的数据的数据线和数据写入和读取电路 连接到所述数据线。 半导体存储器具有多级存储结构。 具体而言，该存储器包括用于按时间序列依次将至少3级以上的不同电压施加到所述存储单元的开关型MOS晶体管的栅极的装置，作为所述数据读取电路的偏置电荷供给装置 以及提供临时存储所述数据的至少两个或更多个存储单元的列寄存器。

    Semiconductor memory having error correcting means
    3.
    发明授权
    Semiconductor memory having error correcting means 失效
    具有误差校正装置的半导体存储器

    公开(公告)号：US4726021A

    公开(公告)日：1988-02-16

    申请号：US853230

    申请日：1986-04-17

    申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    IPC分类号： G06F11/10 ,  G11C29/24 ,  G01R31/28

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C29/24

    摘要： A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease. In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data. To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other.

    摘要翻译： 提供了具有纠错功能的半导体存储器，其具有用户不用利用半导体存储器并且可以容易地进行测试的装置。 在半导体存储器中，从存储器输出表示完成读/写准备的信号，使得用户在检测到该信号的输出之后，执行读/写数据。 为了便于诸如用于冗余位（校验位）的存储器单元测试，编码电路测试和解码电路测试的测试，本发明提供了可以彼此独立地进行布置的测试。

    Semiconductor memory having charge transfer device voltage amplifier
    5.
    发明授权
    Semiconductor memory having charge transfer device voltage amplifier 失效
    具有电荷转移装置电压放大器的半导体存储器

    公开(公告)号：US4636985A

    公开(公告)日：1987-01-13

    申请号：US648361

    申请日：1984-09-07

    申请人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masahi Horiguchi ,  Toshifumi Ozaki ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

    发明人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masahi Horiguchi ,  Toshifumi Ozaki ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

    IPC分类号： G11C7/06 ,  G11C7/22 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/06 ,  H01L27/108

    摘要： In a semiconductor memory in which a large number of memory cells are arrayed in the shape of a matrix, arrangements are provided for a high-sensitivity read-out. In one embodiment, a writing circuit, a voltage amplifier and a sense amplifier are successively connected to a data line that connects input and output ends of the memory cells in an identical row, with the voltage amplifier being formed as a CTD voltage amplifier that is composed of two charge transfer gates and a driving gate located between them. In accordance with another embodiment, a charge supplying circuit and a charge transfer circuit can be coupled between the memory cells and the sense amplifier to allow information transfer without any substantial loss.

    摘要翻译： 在其中以矩阵形式排列大量存储单元的半导体存储器中，提供了用于高灵敏度读出的布置。 在一个实施例中，写入电路，电压放大器和读出放大器连续地连接到连接存储器单元的输入和输出端相同行的数据线，电压放大器形成为CTD电压放大器 由两个电荷转移门和位于它们之间的驱动门组成。 根据另一个实施例，电荷供应电路和电荷转移电路可以耦合在存储器单元和读出放大器之间以允许信息传输而没有任何实质的损失。

    Semiconductor memory device having flip-flop circuits
    10.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US5132771A

    公开(公告)日：1992-07-21

    申请号：US503928

    申请日：1990-04-04

    申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

    IPC分类号： G11C11/412 ,  H01L27/11

    CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

    摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

    摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。