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    NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME 审中-公开
    非易失性存储元件及其制造方法

    公开(公告)号：US20090206393A1

    公开(公告)日：2009-08-20

    申请号：US12388040

    申请日：2009-02-18

    申请人： Keiko Ariyoshi ,  Akira Takashima ,  Shoko Kikuchi ,  Koichi Muraoka

    发明人： Keiko Ariyoshi ,  Akira Takashima ,  Shoko Kikuchi ,  Koichi Muraoka

    IPC分类号： H01L29/792 ,  H01L21/28

    CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513

    摘要： A nonvolatile memory element includes a semiconductor region, a source region and a drain region provided in the semiconductor region, a tunnel insulating layer provided on the semiconductor region between the source region and the drain region, a charge storage layer provided on the tunnel insulating layer, a block insulating layer provided on the charge storage layer, and a control gate electrode provided on the block insulating layer. The charge storage layer includes one of an oxide, a nitride and an oxynitride, which contains at least one material selected from the group consisting of Hf, Al, Zr, Ti and a rare-earth metal, and is entirely or partially crystallized. The block insulating layer includes one of an oxide, an oxynitride, a silicate and an aluminate, which contains at least one rare-earth metal.

    摘要翻译： 非易失性存储元件包括设置在半导体区域中的半导体区域，源极区域和漏极区域，设置在源极区域和漏极区域之间的半导体区域上的隧道绝缘层，设置在隧道绝缘层上的电荷存储层 设置在电荷存储层上的块绝缘层和设置在块绝缘层上的控制栅电极。 电荷存储层包括氧化物，氮化物和氧氮化物中的一种，其含有选自Hf，Al，Zr，Ti和稀土金属中的至少一种材料，并且完全或部分结晶。 该块绝缘层包含含有至少一种稀土金属的氧化物，氮氧化物，硅酸盐和铝酸盐中的一种。

    Nonvolatile semiconductor memory device
    4.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07804128B2

    公开(公告)日：2010-09-28

    申请号：US12199036

    申请日：2008-08-27

    申请人： Keiko Ariyoshi ,  Akira Takashima ,  Shoko Kikuchi ,  Koichi Muraoka

    发明人： Keiko Ariyoshi ,  Akira Takashima ,  Shoko Kikuchi ,  Koichi Muraoka

    IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

    摘要： A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si.

    摘要翻译： 根据本发明实施例的非易失性半导体存储器件包括半导体区域，在半导体区域中单独布置的源极/漏极区域，布置在源极/漏极区域之间的沟道区域上的隧道绝缘膜，布置成 在隧道绝缘膜上，布置在浮栅电极上的电极间绝缘膜和布置在电极间绝缘膜上的控制栅电极。 电极间绝缘膜包括La，Al和Si。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体存储器件及其制造方法

    公开(公告)号：US20100032747A1

    公开(公告)日：2010-02-11

    申请号：US12506534

    申请日：2009-07-21

    申请人： Takayuki OKAMURA ,  Keiko Ariyoshi

    发明人： Takayuki OKAMURA ,  Keiko Ariyoshi

    IPC分类号： H01L29/792 ,  H01L21/28

    CPC分类号： H01L27/11521 ,  H01L27/11524

    摘要： A semiconductor memory device includes a plurality of memory cell transistors each having a gate electrode section including a charge accumulation layer formed on a semiconductor substrate via a gate insulating film, a first insulating film formed using a material with a higher dielectric constant than the gate insulating film, a control gate, an impurity diffusion layer functioning as a source or a drain, and a plurality of barrier films formed on a side surface of the gate electrode section so as to cover a side surface of at least the first insulating film and formed between the first insulating film and the control gate. The device further includes a plurality of second insulating films formed on the semiconductor substrate and each formed between the gate electrode sections of adjacent ones of the plurality of memory cell transistors.

    摘要翻译： 半导体存储器件包括多个存储单元晶体管，每个存储单元晶体管具有通过栅极绝缘膜形成在半导体衬底上的电荷累积层的栅极部分，使用具有比绝缘栅极更高的介电常数的材料形成的第一绝缘膜 膜，控制栅极，用作源极或漏极的杂质扩散层，以及形成在栅电极部分的侧表面上的多个阻挡膜，以覆盖至少第一绝缘膜的侧表面并形成 在第一绝缘膜和控制栅之间。 该器件还包括多个第二绝缘膜，形成在半导体衬底上并且各自形成在多个存储单元晶体管中的相邻栅极电极部分之间。

    Semiconductor device and method for manufacturing the same
    6.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08941120B2

    公开(公告)日：2015-01-27

    申请号：US13715204

    申请日：2012-12-14

    申请人： Keiko Ariyoshi ,  Takuma Suzuki ,  Takashi Shinohe

    发明人： Keiko Ariyoshi ,  Takuma Suzuki ,  Takashi Shinohe

    IPC分类号： H01L29/15 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L21/04 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49

    CPC分类号： H01L29/4236 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/4975 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

    摘要： According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide.

    摘要翻译： 根据一个实施例，半导体器件包括第一，第二，第三，第四半导体区域，控制电极和绝缘膜。 第一区域包含碳化硅。 第二区域设置在第一区域上并且包含碳化硅。 第三区域设置在第二区域上并且包含碳化硅。 第四区域设置在第三区域并且包含碳化硅。 控制电极设置在沟槽中。 沟槽形成在第四，第三和第二半导体区域中。 绝缘膜设置在沟槽的侧表面和控制电极之间。 绝缘膜包含高介电常数区域。 高介电常数区域与至少第三半导体区域接触。 高介电常数区域的介电常数比氧化硅介电常数高。