公开(公告)号：US08629526B2

公开(公告)日：2014-01-14

申请号：US13233941

申请日：2011-09-15

申请人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki

发明人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki

IPC分类号： H01L29/47

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/36 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type and a first electrode. The second regions are provided separately on a first major surface side of the first layer. The third region is provided on the first major surface side of the first layer so as to surround the second regions. The first electrode is provided on the first layer and the second regions. The first layer has a first portion and a second portion. The second portion has a lower resistivity than the first portion. The second portion is provided between the second regions and between the first portion and the first major surface and is provided outside the third region and between the first portion and the first major surface.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第二导电类型的多个第二半导体区域，第二导电类型的第三半导体区域和第一电极。 第二区域分别设置在第一层的第一主表面侧。 第三区域设置在第一层的第一主表面侧，以围绕第二区域。 第一电极设置在第一层和第二区域上。 第一层具有第一部分和第二部分。 第二部分具有比第一部分更低的电阻率。 第二部分设置在第二区域之间以及第一部分与第一主表面之间，并且设置在第三区域的外部以及第一部分与第一主表面之间。

公开(公告)号：US20120241853A1

公开(公告)日：2012-09-27

申请号：US13236588

申请日：2011-09-19

申请人： Tsuyoshi OHTA ,  Masatoshi Arai ,  Miwako Suzuki

发明人： Tsuyoshi OHTA ,  Masatoshi Arai ,  Miwako Suzuki

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

摘要翻译： 半导体层具有第二杂质浓度。 第一沟槽形成在半导体层中，从半导体层的上表面向下延伸。 每个绝缘层沿着第一沟槽的每个内壁形成。 每个导电层被形成为经由每个绝缘层埋入每个第一沟槽，并且从半导体层的上表面向下延伸到第一位置。 第一半导体扩散层从半导体层的上表面到达第二位置，位于第一沟槽之间，并且具有低于第二杂质浓度的第三杂质浓度。 从半导体层的上表面到第二位置的长度等于或小于从半导体层的上表面到第一位置的一半长度。

公开(公告)号：US08723253B2

公开(公告)日：2014-05-13

申请号：US13239101

申请日：2011-09-21

申请人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki

发明人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0856 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8725

摘要： According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.

摘要翻译： 根据一个实施例，半导体器件包括第一半导体层。 所述半导体器件包括多个基极区域，所述基极区域设置在所述第一半导体层的表面上。 半导体器件包括选择性地设置在基极区域的每个表面上的源极区域。 半导体器件包括在一对沟槽中的每一个中经由栅极绝缘膜提供的栅电极，每个沟槽从源极区域的表面到第一半导体层穿透基极区域。 半导体器件包括在栅电极下的一对沟槽中的每一个中经由场板绝缘膜设置的场板电极。 场板绝缘膜的一部分的厚度大于栅极绝缘膜的厚度。

公开(公告)号：US08552476B2

公开(公告)日：2013-10-08

申请号：US13236588

申请日：2011-09-19

申请人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki

发明人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki

IPC分类号： H01L29/80 ,  H01L29/66 ,  H01L29/76 ,  H01L29/47

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

摘要翻译： 半导体层具有第二杂质浓度。 第一沟槽形成在半导体层中，从半导体层的上表面向下延伸。 每个绝缘层沿着第一沟槽的每个内壁形成。 每个导电层被形成为经由每个绝缘层埋入每个第一沟槽，并且从半导体层的上表面向下延伸到第一位置。 第一半导体扩散层从半导体层的上表面到达第二位置，位于第一沟槽之间，并且具有低于第二杂质浓度的第三杂质浓度。 从半导体层的上表面到第二位置的长度等于或小于从半导体层的上表面到第一位置的一半长度。

公开(公告)号：US20120241898A1

公开(公告)日：2012-09-27

申请号：US13419395

申请日：2012-03-13

申请人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki ,  Tadashi Matsuda

发明人： Tsuyoshi Ohta ,  Masatoshi Arai ,  Miwako Suzuki ,  Tadashi Matsuda

IPC分类号： H01L29/47

CPC分类号： H01L29/66136 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872 ,  H01L29/8725

摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of the first conductivity type and a second electrode. The first semiconductor region includes a first portion including a first major surface and a second portion extending in a first direction perpendicular to the first major surface on the first major surface. The first electrode includes a third portion provided to face the second portion and is provided to be separated from the first semiconductor region. The second semiconductor region is provided between the second and third portions, includes a first concentration region having a lower impurity concentration than the first semiconductor region and forms a Schottky junction with the third portion. The second electrode is provided on an opposite side of the first major surface and in conduction with the first portion.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一电极，第一导电类型的第二半导体区域和第二电极。 第一半导体区域包括包括第一主表面的第一部分和在垂直于第一主表面上的第一主表面的第一方向上延伸的第二部分。 第一电极包括设置成面对第二部分的第三部分，并且设置成与第一半导体区域分离。 第二半导体区域设置在第二和第三部分之间，包括具有比第一半导体区域低的杂质浓度的第一浓度区域，并与第三部分形成肖特基结。 第二电极设置在第一主表面的相反侧并与第一部分导通。

公开(公告)号：US20120241854A1

公开(公告)日：2012-09-27

申请号：US13239101

申请日：2011-09-21

申请人： Tsuyoshi OHTA ,  Masatoshi Arai ,  Miwako Suzuki

发明人： Tsuyoshi OHTA ,  Masatoshi Arai ,  Miwako Suzuki

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0856 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/861 ,  H01L29/8725

摘要： According to one embodiment, the semiconductor device includes a first semiconductor layer. The semiconductor device includes a plurality of base regions, the base regions are provided on a surface of the first semiconductor layer. The semiconductor device includes a source region selectively provided on each of surfaces of the base regions. The semiconductor device includes a gate electrode provided via a gate insulating film in each of a pair of trenches, each of the trenches penetrate the base regions from a surface of the source region to the first semiconductor layer. The semiconductor device includes a field plate electrode provided via a field plate insulating film in each of the pair of trenches under the gate electrode. A thickness of a part of the field plate insulating film is greater than a thickness of the gate insulating film.

摘要翻译： 根据一个实施例，半导体器件包括第一半导体层。 所述半导体器件包括多个基极区域，所述基极区域设置在所述第一半导体层的表面上。 半导体器件包括选择性地设置在基极区域的每个表面上的源极区域。 半导体器件包括在一对沟槽中的每一个中经由栅极绝缘膜提供的栅电极，每个沟槽从源极区域的表面到第一半导体层穿透基极区域。 半导体器件包括在栅电极下的一对沟槽中的每一个中经由场板绝缘膜设置的场板电极。 场板绝缘膜的一部分的厚度大于栅极绝缘膜的厚度。

公开(公告)号：US08502305B2

公开(公告)日：2013-08-06

申请号：US13421816

申请日：2012-03-15

申请人： Tsuyoshi Ohta ,  Tatsuya Nishiwaki ,  Norio Yasuhara ,  Masatoshi Arai ,  Takahiro Kawano

发明人： Tsuyoshi Ohta ,  Tatsuya Nishiwaki ,  Norio Yasuhara ,  Masatoshi Arai ,  Takahiro Kawano

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/2255 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734 ,  H01L29/861

摘要： According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.

摘要翻译： 根据实施例，半导体器件包括第一导电类型的半导体层，设置在半导体层上的第二导电类型的基极区域和设置在基极区域上的第二导电类型的第一接触区域。 该器件包括设置在穿过第一接触区域和基极区域的沟槽中的栅电极，以及设置在栅极上并包含第一导电型杂质元素的层间绝缘膜。 该器件还包括设置在层间绝缘膜和第一接触区域之间的第一导电类型的源极区域，源极区域与层间绝缘膜的侧面接触并且在基极区域中延伸。

公开(公告)号：US08576319B2

公开(公告)日：2013-11-05

申请号：US12929004

申请日：2010-12-22

申请人： Masatoshi Kureta ,  Masatoshi Arai ,  Takeharu Etoh ,  Konoe Etoh ,  Toshiaki Akino

发明人： Masatoshi Kureta ,  Masatoshi Arai ,  Takeharu Etoh ,  Konoe Etoh ,  Toshiaki Akino

IPC分类号： H04N3/14 ,  H04N5/335 ,  H04N9/04

CPC分类号： H04N5/335 ,  H01L27/14806 ,  H04N5/3592 ,  H04N5/37213 ,  H04N5/3728

摘要： An image sensor and an image sensing method can obtain image signals with a high S/N ratio in a high-speed image pickup operation. Signal charges are input to input transfer stage 31 of CCD memory 30. Final transfer stage 32 is formed so as to be connected to the input transfer stage 31 and able to transfer signal charges to the input transfer stage 31. In an accumulation mode, read gate 42 and drain gate 40 are not turned on and the next transfer operation of the CCD memory 30 is conducted. The accumulated signal charges are transferred on a stage by stage basis and the signal charges obtained at the first image pickup timing are transferred again straightly to the input transfer stage 31. In this state, the signal charges obtained newly at photoelectric conversion section 20 at the next image pickup timing are injected into the input transfer stage 31 by way of input gate 21. As a result of this operation, the signal charges obtained at the last image pickup timing are added to the signal charges accumulated in the input transfer stage 31 so that integrated signal charges obtained by adding the two sets of signal charges are accumulated in the input transfer stage 31.

摘要翻译： 图像传感器和图像感测方法可以在高速图像拾取操作中获得具有高S / N比的图像信号。 信号电荷被输入到CCD存储器30的输入传送级31.最终传送级32被形成为连接到输入传送级31并且能够将信号电荷传送到输入传送级31.在累加模式下，读取 门42和漏极门40不导通，并且进行CCD存储器30的下一个传送操作。 累积的信号电荷逐级传送，并且在第一摄像定时获得的信号电荷被直接传送到输入传送级31.在这种状态下，在光电转换部20新获得的信号电荷 下一个图像拾取定时通过输入门21被注入到输入传送级31.作为该操作的结果，在最后图像拾取定时获得的信号电荷被加到累积在输入传送级31中的信号电荷 通过添加两组信号电荷而获得的积分信号电荷被积累在输入传送级31中。

公开(公告)号：US20130248995A1

公开(公告)日：2013-09-26

申请号：US13607533

申请日：2012-09-07

申请人： Tatsuya NISHIWAKI ,  Tsuyoshi Ota ,  Norio Yasuhara ,  Masatoshi Arai ,  Takahiro Kawano

发明人： Tatsuya NISHIWAKI ,  Tsuyoshi Ota ,  Norio Yasuhara ,  Masatoshi Arai ,  Takahiro Kawano

IPC分类号： H01L29/78 ,  H01L21/82 ,  H01L27/088

CPC分类号： H01L29/7827 ,  H01L21/82 ,  H01L27/088 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type placed above the first semiconductor layer, a second semiconductor layer of the first conductivity type placed above the base layer, multiple gate electrodes having upper end is positioned above the upper surface of the base layer, a lower end positioned below the bottom of the base layer, and contacting the first semiconductor layer, the second semiconductor layer, and the base layer through a gate insulating film, insulating component arranged above the gate electrode in which the upper surface is positioned below the upper surface of the second semiconductor layer, and a conductive layer covering the second semiconductor layer from the upper end to the bottom end.

摘要翻译： 半导体器件包括第一导电类型的第一半导体层，位于第一半导体层上方的第二导电类型的基极层，位于基极层之上的第一导电类型的第二半导体层，具有上端的多个栅电极 位于所述基底层的上表面的上方，位于所述基底层的底部下方的下端，并且通过栅极绝缘膜与所述第一半导体层，所述第二半导体层和所述基底层接触， 栅电极，其上表面位于第二半导体层的上表面下方，以及导电层，其从上端到底端覆盖第二半导体层。

公开(公告)号：US20120270155A1

公开(公告)日：2012-10-25

申请号：US13449727

申请日：2012-04-18

申请人： Yoshitaka Komuro ,  Yoshiyuki Utsumi ,  Akiya Kawaue ,  Masatoshi Arai

发明人： Yoshitaka Komuro ,  Yoshiyuki Utsumi ,  Akiya Kawaue ,  Masatoshi Arai

IPC分类号： C07C309/23 ,  C07D327/04 ,  G03F7/20 ,  C07D493/18 ,  C08F128/02 ,  G03F7/027

CPC分类号： C07C381/12 ,  C07C309/12 ,  C07C309/19 ,  C07C309/42 ,  C07C309/43 ,  C07C311/09 ,  C07C311/48 ,  C07C2601/08 ,  C07C2601/14 ,  C07C2602/42 ,  C07C2603/74 ,  C07D307/93 ,  C07D493/18 ,  C08F220/28 ,  C08F228/02 ,  G03F7/0045 ,  G03F7/0046 ,  G03F7/039 ,  G03F7/0397 ,  G03F7/2041 ,  Y10S430/115 ,  Y10S430/122 ,  Y10S522/904

摘要： There are provided a novel compound, a polymeric compound, a resist composition, an acid generator and a method of forming a resist pattern the compound represented by general formula (1-1): wherein each of R1 and R3 independently represents a single bond or a divalent linking group; A represents a divalent linking group; each of R2 and R4 independently represents a hydroxyl group, a hydrocarbon group which may have a substituent, or a group represented by general formula (1-an1), (1-an2) or (1-an3), provided that at least one of R2 and R4 represents a group represented by general formula (1-an1), (1-an2) or (1-an3); and n0 is preferably 0 or 1, and wherein Y1 represents a single bond or —SO2—; R5 represents a linear or branched monovalent hydrocarbon group of 1 to 10 carbon atoms, cyclic monovalent hydrocarbon group of 3 to 20 carbon atoms or monovalent hydrocarbon group of 3 to 20 carbon atoms having a cyclic partial structure which may be substituted with a fluorine atom; and M+ represents an organic cation or a metal cation,

摘要翻译： 提供了一种新型化合物，高分子化合物，抗蚀剂组合物，酸产生剂和由通式（1-1）表示的化合物形成抗蚀剂图案的方法：其中R 1和R 3各自独立地表示单键或 二价连接基团; A表示二价连接基团; R2和R4各自独立地表示羟基，可以具有取代基的烃基或由通式（1-an1），（1-an2）或（1-an3）表示的基团），条件是至少一个 R 2和R 4表示由通式（1-an1），（1-an2）或（1-an3）表示的基团。 n0优选为0或1，并且其中Y1表示单键或-SO2-; R5表示1〜10个碳原子的直链或支链一价烃基，3〜20个碳原子的环状一价烃基或具有可被氟原子取代的环状部分结构的3〜20个碳原子的一价烃基; M +表示有机阳离子或金属阳离子，