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    Image sensor and manufacturing method thereof
    1.
    发明公开
    Image sensor and manufacturing method thereof 审中-公开

    公开(公告)号：US20230225139A1

    公开(公告)日：2023-07-13

    申请号：US18122718

    申请日：2023-03-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zhaoyao Zhan ,  QIANWEI DING ,  XIAOHONG JIANG ,  CHING HWA TEY

    IPC: H10K39/32 ,  H10K85/50

    CPC classification number: H10K39/32 ,  H10K85/50

    Abstract: The present invention provides an image sensor, the image sensor includes a substrate, a first circuit layer on the substrate, at least one nanowire photodiode located on the first circuit layer and electrically connected with the first circuit layer, wherein the nanowire photodiode comprises a lower material layer and an upper material layer, and a P-N junction or a Schottky junction is arranged between the lower material layer and the upper material layer, wherein the lower material layer comprises a perovskite material, and a precursor layer located under the lower material layer, wherein the precursor layer comprises different metal elements as the lower material layer

    SEMICONDUCTOR PROCESS
    3.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20150348789A1

    公开(公告)日：2015-12-03

    申请号：US14288399

    申请日：2014-05-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Duan Quan Liao ,  Wei Cheng ,  Yikun Chen ,  CHING HWA TEY ,  Xiao Zhong Zhu

    IPC: H01L21/28

    CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11534

    Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

    Abstract translation: 半导体工艺包括以下步骤。 第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。 形成间隔物材料以保形地覆盖第一栅极和衬底。 蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。 材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。 块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

    PHOTOSENSITIVE DEVICE
    4.
    发明申请
    PHOTOSENSITIVE DEVICE 有权

    公开(公告)号：US20210384231A1

    公开(公告)日：2021-12-09

    申请号：US16931400

    申请日：2020-07-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zhaoyao Zhan ,  QIANWEI DING ,  XIAOHONG JIANG ,  CHING HWA TEY

    IPC: H01L27/146

    Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a photodiode.

    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20170040179A1

    公开(公告)日：2017-02-09

    申请号：US14838374

    申请日：2015-08-28

    Applicant: United Microelectronics Corp.

    Inventor： Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

    IPC: H01L21/3105 ,  H01L21/32 ,  H01L21/768 ,  H01L21/283

    CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/76829 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first hard mask atop the gate structure, and an interlayer dielectric (ILD) layer around the gate structure and the first hard mask; removing part of the first hard mask; forming a second hard mask layer on the first hard mask and the ILD layer; and planarizing part of the second hard mask layer to form a second hard mask on the first hard mask.

    Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，栅极结构顶部的第一硬掩模和围绕栅极结构和第一硬掩模的层间电介质（ILD）层; 去除第一硬掩模的一部分; 在所述第一硬掩模和所述ILD层上形成第二硬掩模层; 以及平坦化所述第二硬掩模层的部分以在所述第一硬掩模上形成第二硬掩模。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20170025519A1

    公开(公告)日：2017-01-26

    申请号：US14829649

    申请日：2015-08-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

    IPC: H01L29/66 ,  H01L23/535 ,  H01L29/06 ,  H01L21/768

    CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/0657 ,  H01L29/66553

    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

    Abstract translation: 半导体器件及其制造方法，半导体器件包括硬掩模层和多个间隔物。 硬掩模层设置在目标层上并具有第一材料和第二材料。 间隔物设置在硬掩模层上，其中间隔物的第一部分设置在第一材料上，间隔物的第二部分设置在第二材料上。

    TRANSISTOR STRUCTURE WITH AIR GAP AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    TRANSISTOR STRUCTURE WITH AIR GAP AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220262671A1

    公开(公告)日：2022-08-18

    申请号：US17737011

    申请日：2022-05-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yunfei Li ,  JI FENG ,  GUOHAI ZHANG ,  CHING HWA TEY

    IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L21/02

    Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

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