公开(公告)号：US20060057832A1

公开(公告)日：2006-03-16

申请号：US10938239

申请日：2004-09-10

申请人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Rotaru ,  Tai Chong Chai ,  Mahadevan Iyer

发明人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Rotaru ,  Tai Chong Chai ,  Mahadevan Iyer

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/5222 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/013

摘要： A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

摘要翻译： 公开了一种形成在具有接合垫的集成电路芯片上的晶片级封装及其制造方法。 晶片级封装包括至少一个第一，第二和第三分离层，其具有形成在分离层之间的至少一个第一和第二导电层。 所述至少一个第一导电层形成在所述至少一个第一分离层上并且耦合到所述粘合垫。 至少一个第二导电层形成在最后一个第二分离层上，其中至少一个第二导电层电耦合到至少一个第一导电层。 所述至少一个第三分离层允许将焊料附着到所述至少一个第二导电层，以将所述焊料电耦合到所述粘合垫。 集成电路芯片中放置有芯片接地层，用于向至少一个第一导电层和焊料提供接地。

公开(公告)号：US07189594B2

公开(公告)日：2007-03-13

申请号：US10938239

申请日：2004-09-10

申请人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Dragos Rotaru ,  Tai Chong Chai ,  Mahadevan Krishna Iyer

发明人： Vaidyanathan Kripesh ,  Wai Kwan Wong ,  Mihai Dragos Rotaru ,  Tai Chong Chai ,  Mahadevan Krishna Iyer

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L23/5222 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/013

摘要： A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.

摘要翻译： 公开了一种形成在具有接合垫的集成电路芯片上的晶片级封装及其制造方法。 晶片级封装包括至少一个第一，第二和第三分离层，其具有形成在分离层之间的至少一个第一和第二导电层。 所述至少一个第一导电层形成在所述至少一个第一分离层上并且耦合到所述粘合垫。 至少一个第二导电层形成在最后一个第二分离层上，其中至少一个第二导电层电耦合到至少一个第一导电层。 所述至少一个第三分离层允许将焊料附着到所述至少一个第二导电层，以将所述焊料电耦合到所述粘合垫。 集成电路芯片中放置有芯片接地层，用于向至少一个第一导电层和焊料提供接地。

公开(公告)号：US07178711B2

公开(公告)日：2007-02-20

申请号：US10667008

申请日：2003-09-17

申请人： Ee Hua Wong ,  Ranjan Rajoo ,  Wai Kwan Wong ,  Mahadevan Krishna Iyer

发明人： Ee Hua Wong ,  Ranjan Rajoo ,  Wai Kwan Wong ,  Mahadevan Krishna Iyer

IPC分类号： B23K31/02

CPC分类号： H05K3/303 ,  B23K31/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H05K3/3436 ,  H05K2201/0129 ,  H05K2201/0311 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/0465 ,  H05K2203/1105 ,  H05K2203/306 ,  Y02P70/613 ,  H01L2224/81

摘要： A method and device to elongate a solder joint are provided. The method begins by forming an elongator on a first substrate. The elongator comprises an expander and an encapsulant to encapsulate the expander. A solder joint is formed to connect the first substrate to a second substrate. Thereafter, the encapsulant is softened to release the expander from a compressed state to elongate the solder joint. The device to elongate a solder joint comprises a substrate having an elongator formed on it. The elongator includes an expander in a compressed state and an encapsulant to encapsulate the expander.

公开(公告)号：US07453154B2

公开(公告)日：2008-11-18

申请号：US11391852

申请日：2006-03-29

申请人： Kiat Choon Teo ,  Wai Kwan Wong ,  Binghua Pan

发明人： Kiat Choon Teo ,  Wai Kwan Wong ,  Binghua Pan

IPC分类号： H01L21/44

CPC分类号： H05K3/4007 ,  B81C1/00095 ,  B82Y10/00 ,  H01L23/49827 ,  H01L23/49877 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/274 ,  H01L2224/81136 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K2201/026 ,  Y02P70/613 ,  H01L2924/00014

摘要： An electronic device that facilitates improved electrical and thermal performance and/or allows fabrication of smaller electronic devices exhibiting excellent performance characteristics, especially for devices operating at microwave frequencies, includes an input/output pad, and a carbon nanotube extending from the input/output pad to provide wafer-level nano-interconnect for flip chip interconnections and die stacking on a substrate.

摘要翻译： 有助于改善电气和热性能和/或允许制造具有优异性能特征的较小电子器件的电子器件，特别是对于以微波频率工作的器件，包括输入/​​输出焊盘和从输入/输出焊盘延伸的碳纳米管 以提供用于倒装芯片互连和芯片堆叠在衬底上的晶片级纳米互连。