Viscous electropolishing system
    1.
    发明授权
    Viscous electropolishing system 失效
    粘性电解抛光系统

    公开(公告)号:US06935933B1

    公开(公告)日:2005-08-30

    申请号:US10036621

    申请日:2001-12-21

    摘要: A method for planarizing a surface of an electrically conductive layer on a substrate, where the surface of the electrically conductive layer has relatively high features and relatively low features. A viscous material is applied to the surface of the electrically conductive layer, whereby at least the relatively low features are covered by the viscous material. The substrate is immersed in an electrically conductive solution. An electrical potential is applied between the electrically conductive layer and an electrode within the electrically conductive solution, whereby reaction kinetics favor erosion of the electrically conductive layer. The electrically conductive solution is agitated, thereby selectively uncovering the viscous material from at least features that are relatively high, and thereby preferentially planarizing at least the features that are relatively high.

    摘要翻译: 一种用于平坦化基板上的导电层的表面的方法,其中导电层的表面具有相对较高的特征和相对较低的特征。 将粘性材料施加到导电层的表面,由此至少相对较低的特征被粘性材料覆盖。 将基板浸入导电溶液中。 在导电溶液中的导电层和电极之间施加电位,由此反应动力学有利于导电层的侵蚀。 搅动导电溶液,从而从至少相对高的特征选择性地露出粘性材料,从而优先至少平坦化至少相对高的特征。

    Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
    3.
    发明授权
    Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures 有权
    用于增加铜互连结构中的电迁移寿命的介电阻挡层

    公开(公告)号:US08043968B2

    公开(公告)日:2011-10-25

    申请号:US12764004

    申请日:2010-04-20

    IPC分类号: H01L21/00

    摘要: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

    摘要翻译: 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分,第一部分具有相对于第二部分提高的对铜的粘附性,并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着,以增加堆叠中这种材料的浓度。

    Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface
    4.
    发明授权
    Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface 有权
    一种用于形成集成电路结构的方法,其包括在上表面具有抗反射特性的低k电介质材料层

    公开(公告)号:US06613665B1

    公开(公告)日:2003-09-02

    申请号:US10002981

    申请日:2001-10-26

    IPC分类号: H01L214763

    摘要: A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.

    摘要翻译: 公开了一种用于形成集成电路结构的方法,其特征在于形成组合的电介质层和抗反射涂层。 该方法包括在集成电路结构上形成介电材料层,以及处理介电材料层的表面以在其中形成抗反射涂层(ARC)表面。 当然后在ARC表面上形成一层光致抗蚀剂,并且光致抗蚀剂层暴露于辐射图形时,ARC表面提高了光致抗蚀剂层中辐射图案复制的准确性。 优选地,用包含元素和/或化合物的离子的等离子体处理介电层的表面以形成ARC表面。

    Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures
    5.
    发明授权
    Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures 有权
    在集成电路结构中的铜金属化的至少一个低介电常数绝缘层中形成的开口的等离子体清洁工艺

    公开(公告)号:US06204192B1

    公开(公告)日:2001-03-20

    申请号:US09281602

    申请日:1999-03-29

    IPC分类号: H01L2100

    摘要: A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.

    摘要翻译: 提供了一种用于从集成电路结构的铜金属互连层上去除在低介电常数绝缘材料的一层或多层中形成的一个或多个开口的蚀刻残留物的工艺,其包括清洁铜互连层的表面的暴露部分 在一个或多个开口的底部,该方法包括提供各向异性氢等离子体以引起等离子体中的离子与一个或多个开口底部的蚀刻残留物(包括暴露的铜表面上的氧化铜)的化学反应 ,从而清洁铜表面的暴露部分,并且在不溅射开口底部的铜的情况下除去蚀刻残留物。

    Metal-filled via/contact opening with thin barrier layers in integrated
circuit structure for fast response, and process for making same
    6.
    发明授权
    Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same 失效
    金属填充通孔/接触开口,具有集成电路结构中的薄势垒层,用于快速响应,以及制造方法

    公开(公告)号:US5994775A

    公开(公告)日:1999-11-30

    申请号:US932614

    申请日:1997-09-17

    摘要: The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surfaces of the via/contact opening to provide adherence of the filler material to the underlying and sidewall surface of the opening; a CVD barrier layer of tungsten, having a thickness of about 50 Angstroms, but not exceeding about 300 Angstroms, formed over the titanium nitride layer; and the remainder of the via/contact opening filled with a highly conductive metal selected from the group consisting of copper, CVD aluminum, and force-filled aluminum.

    摘要翻译: 本发明包括集成电路结构及其制造方法,其包括介电层中的通孔/接触开口; 在通孔/接触开口的侧壁和底表面上具有至少约50埃但不超过约200埃的厚度的氮化钛的CVD层,以提供填充材料对下层和侧壁表面的附着 开口 在氮化钛层上形成厚度为约50埃,但不超过约300埃的钨的CVD阻挡层; 并且通孔/接触开口的其余部分填充有选自铜,CVD铝和强力填充铝的高导电性金属。

    Low stress, highly conformal CVD metal thin film
    7.
    发明授权
    Low stress, highly conformal CVD metal thin film 失效
    低应力,高保形CVD金属薄膜

    公开(公告)号:US5953631A

    公开(公告)日:1999-09-14

    申请号:US592870

    申请日:1996-01-24

    IPC分类号: H01L21/768 H01L21/44

    CPC分类号: H01L21/76843

    摘要: A method is presented for depositing a low stress, highly conformal metal thin film, such as tungsten, on a substrate. A substrate is provided, and is heated to a first temperature. A first portion of the metal thin film is deposited on the substrate by reacting a first set of process gases. The deposition of the first portion of the metal thin film is stopped after a first length of time, and the substrate is heated to a second temperature, which is greater than the first temperature. A second portion of the metal thin film is deposited on the substrate by reacting a second set of process gases. The second portion of the metal thin film comprises the same metal as the first portion of the metal thin film. The deposition of the second portion of the metal thin film is stopped after a second length of time. Semiconductor devices having a low stress, highly conformal thin film are also described.

    摘要翻译: 提出了一种在衬底上沉积低应力,高保形金属薄膜(如钨)的方法。 提供基板,并加热至第一温度。 通过使第一组工艺气体反应,将金属薄膜的第一部分沉积在衬底上。 金属薄膜的第一部分的沉积在第一时间段之后停止,并且将基板加热到大于第一温度的第二温度。 金属薄膜的第二部分通过使第二组工艺气体反应而沉积在衬底上。 金属薄膜的第二部分包含与金属薄膜的第一部分相同的金属。 金属薄膜的第二部分的沉积在第二时间长度之后停止。 还描述了具有低应力,高保形薄膜的半导体器件。

    Method for eliminating peeling at end of semiconductor substrate in
metal organic chemical vapor deposition of titanium nitride
    8.
    发明授权
    Method for eliminating peeling at end of semiconductor substrate in metal organic chemical vapor deposition of titanium nitride 失效
    在氮化钛的金属有机化学气相沉积中消除半导体衬底端部剥离的方法

    公开(公告)号:US5789028A

    公开(公告)日:1998-08-04

    申请号:US811818

    申请日:1997-03-04

    摘要: A process and apparatus are described for inhibiting, but not completely eliminating, the deposition of titanium nitride by MOCVD on the end edge of a semiconductor substrate which comprises directing toward such substrate end edge a flow of one or more deposition-inhibiting gases in a direction which substantially opposes the flow of process gases toward the end edges of the substrate. This flow of deposition-inhibiting gases toward the end edges of the substrate reduces the deposition of the titanium nitride at the end edge of the semiconductor substrate either by directing some of the flow of process gases away from such end edge of the substrate, or by locally diluting such process gases in the region of the deposition chamber adjacent the end edge of the substrate, or by some combination of the foregoing. Such flow of deposition-inhibiting gas or gases may be directed toward the end edge of the substrate by flowing such deposition-inhibiting gas or gases through bores provided in the underlying substrate support pedestal which bores have openings peripherally spaced around the pedestal, adjacent the top of the pedestal, through which such gas or gases then exit beneath the plane of the top surface of the substrate and adjacent the end edge of the substrate.

    摘要翻译: 描述了一种方法和装置,用于通过MOCVD在半导体衬底的端部边缘上抑制但不完全消除氮化钛的沉积,该方法包括将一个或多个沉积抑制气体沿着方向 其基本上反对处理气体朝向基板的端部边缘的流动。 这种沉积抑制气体朝向衬底的端部边缘的流动减少了氮化钛在半导体衬底的端部边缘处的沉积,或者通过将一些工艺气体流从衬底的这种端部边缘引导,或者通过 在邻近衬底的端边缘的沉积室的区域中或通过前述的某些组合来局部稀释这些工艺气体。 这种沉积抑制气体或气体的流动可以通过使这种沉积抑制气体或气体通过设置在下面的基底支撑基座中的孔而被引向衬底的端部边缘,孔中具有围绕基座周向间隔开的开口,邻近顶部 基座的这种气体或气体然后在衬底的顶表面的平面之下离开并且靠近衬底的端边缘。

    Plasma clean with hydrogen gas
    9.
    发明授权
    Plasma clean with hydrogen gas 失效
    用氢气清洗等离子体

    公开(公告)号:US5660682A

    公开(公告)日:1997-08-26

    申请号:US615437

    申请日:1996-03-14

    摘要: A method of removing material from an integrated circuit. The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are energized to form a plasma, and the material is removed from the integrated circuit by reaction of the material with the energized flows of argon and hydrogen to form gaseous products, which are pumped out of the reaction chamber. The plasma and flows of argon and hydrogen are discontinued when a desired amount of material has been removed, and the integrated circuit is removed from the reaction chamber.

    摘要翻译: 从集成电路中去除材料的方法。 将集成电路放置在反应室内,并且将氩气和氢气流引入反应室中,其中氢气流量大于氩气流量。 氩气和氢气的流动被激发以形成等离子体,并且通过材料与激励的氩气和氢气流的反应将材料从集成电路移除,以形成气态产物,其被泵出反应室。 当去除所需量的材料时,停止等离子体和氩气和氢气的流动,并且将集成电路从反应室中取出。

    DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES
    10.
    发明申请
    DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES 有权
    用于增加铜互连结构中电磁寿命的电介质障碍层

    公开(公告)号:US20100200993A1

    公开(公告)日:2010-08-12

    申请号:US12764004

    申请日:2010-04-20

    IPC分类号: H01L23/532 H01L21/31

    摘要: Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

    摘要翻译: 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分,第一部分具有相对于第二部分具有改善的对铜的粘合性,并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着,以增加堆叠中这种材料的浓度。